1MIPS CPU interrupt controller 2 3On MIPS the mips_cpu_irq_of_init() helper can be used to initialize the 8 CPU 4IRQs from a devicetree file and create a irq_domain for IRQ controller. 5 6With the irq_domain in place we can describe how the 8 IRQs are wired to the 7platforms internal interrupt controller cascade. 8 9Below is an example of a platform describing the cascade inside the devicetree 10and the code used to load it inside arch_init_irq(). 11 12Required properties: 13- compatible : Should be "mti,cpu-interrupt-controller" 14 15Example devicetree: 16 cpu-irq: cpu-irq { 17 #address-cells = <0>; 18 19 interrupt-controller; 20 #interrupt-cells = <1>; 21 22 compatible = "mti,cpu-interrupt-controller"; 23 }; 24 25 intc: intc@200 { 26 compatible = "ralink,rt2880-intc"; 27 reg = <0x200 0x100>; 28 29 interrupt-controller; 30 #interrupt-cells = <1>; 31 32 interrupt-parent = <&cpu-irq>; 33 interrupts = <2>; 34 }; 35 36 37Example platform irq.c: 38static struct of_device_id __initdata of_irq_ids[] = { 39 { .compatible = "mti,cpu-interrupt-controller", .data = mips_cpu_irq_of_init }, 40 { .compatible = "ralink,rt2880-intc", .data = intc_of_init }, 41 {}, 42}; 43 44void __init arch_init_irq(void) 45{ 46 of_irq_init(of_irq_ids); 47} 48