xref: /freebsd/sys/contrib/device-tree/Bindings/mfd/mscc,ocelot.yaml (revision 8bab661a3316d8bd9b9fbd11a3b4371b91507bd2) 
1# SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause */
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/mfd/mscc,ocelot.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Ocelot Externally-Controlled Ethernet Switch
8
9maintainers:
10  - Colin Foster <colin.foster@in-advantage.com>
11
12description: |
13  The Ocelot ethernet switch family contains chips that have an internal CPU
14  (VSC7513, VSC7514) and chips that don't (VSC7511, VSC7512). All switches have
15  the option to be controlled externally via external interfaces like SPI or
16  PCIe.
17
18  The switch family is a multi-port networking switch that supports many
19  interfaces. Additionally, the device can perform pin control, MDIO buses, and
20  external GPIO expanders.
21
22properties:
23  compatible:
24    enum:
25      - mscc,vsc7512
26
27  reg:
28    maxItems: 1
29
30  "#address-cells":
31    const: 1
32
33  "#size-cells":
34    const: 1
35
36  spi-max-frequency:
37    maxItems: 1
38
39patternProperties:
40  "^pinctrl@[0-9a-f]+$":
41    type: object
42    $ref: /schemas/pinctrl/mscc,ocelot-pinctrl.yaml
43
44  "^gpio@[0-9a-f]+$":
45    type: object
46    $ref: /schemas/pinctrl/microchip,sparx5-sgpio.yaml
47    properties:
48      compatible:
49        enum:
50          - mscc,ocelot-sgpio
51
52  "^mdio@[0-9a-f]+$":
53    type: object
54    $ref: /schemas/net/mscc,miim.yaml
55    properties:
56      compatible:
57        enum:
58          - mscc,ocelot-miim
59
60required:
61  - compatible
62  - reg
63  - '#address-cells'
64  - '#size-cells'
65
66additionalProperties: false
67
68examples:
69  - |
70    ocelot_clock: ocelot-clock {
71          compatible = "fixed-clock";
72          #clock-cells = <0>;
73          clock-frequency = <125000000>;
74      };
75
76    spi {
77        #address-cells = <1>;
78        #size-cells = <0>;
79
80        soc@0 {
81            compatible = "mscc,vsc7512";
82            spi-max-frequency = <2500000>;
83            reg = <0>;
84            #address-cells = <1>;
85            #size-cells = <1>;
86
87            mdio@7107009c {
88                compatible = "mscc,ocelot-miim";
89                #address-cells = <1>;
90                #size-cells = <0>;
91                reg = <0x7107009c 0x24>;
92
93                sw_phy0: ethernet-phy@0 {
94                    reg = <0x0>;
95                };
96            };
97
98            mdio@710700c0 {
99                compatible = "mscc,ocelot-miim";
100                pinctrl-names = "default";
101                pinctrl-0 = <&miim1_pins>;
102                #address-cells = <1>;
103                #size-cells = <0>;
104                reg = <0x710700c0 0x24>;
105
106                sw_phy4: ethernet-phy@4 {
107                    reg = <0x4>;
108                };
109            };
110
111            gpio: pinctrl@71070034 {
112                compatible = "mscc,ocelot-pinctrl";
113                gpio-controller;
114                #gpio-cells = <2>;
115                gpio-ranges = <&gpio 0 0 22>;
116                reg = <0x71070034 0x6c>;
117
118                sgpio_pins: sgpio-pins {
119                    pins = "GPIO_0", "GPIO_1", "GPIO_2", "GPIO_3";
120                    function = "sg0";
121                };
122
123                miim1_pins: miim1-pins {
124                    pins = "GPIO_14", "GPIO_15";
125                    function = "miim";
126                };
127            };
128
129            gpio@710700f8 {
130                compatible = "mscc,ocelot-sgpio";
131                #address-cells = <1>;
132                #size-cells = <0>;
133                bus-frequency = <12500000>;
134                clocks = <&ocelot_clock>;
135                microchip,sgpio-port-ranges = <0 15>;
136                pinctrl-names = "default";
137                pinctrl-0 = <&sgpio_pins>;
138                reg = <0x710700f8 0x100>;
139
140                sgpio_in0: gpio@0 {
141                    compatible = "microchip,sparx5-sgpio-bank";
142                    reg = <0>;
143                    gpio-controller;
144                    #gpio-cells = <3>;
145                    ngpios = <64>;
146                };
147
148                sgpio_out1: gpio@1 {
149                    compatible = "microchip,sparx5-sgpio-bank";
150                    reg = <1>;
151                    gpio-controller;
152                    #gpio-cells = <3>;
153                    ngpios = <64>;
154                };
155            };
156        };
157    };
158
159...
160
161