1ChromeOS Embedded Controller 2 3Google's ChromeOS EC is a Cortex-M device which talks to the AP and 4implements various function such as keyboard and battery charging. 5 6The EC can be connect through various means (I2C, SPI, LPC, RPMSG) and the 7compatible string used depends on the interface. Each connection method has 8its own driver which connects to the top level interface-agnostic EC driver. 9Other Linux driver (such as cros-ec-keyb for the matrix keyboard) connect to 10the top-level driver. 11 12Required properties (I2C): 13- compatible: "google,cros-ec-i2c" 14- reg: I2C slave address 15 16Required properties (SPI): 17- compatible: "google,cros-ec-spi" 18- reg: SPI chip select 19 20Required properties (RPMSG): 21- compatible: "google,cros-ec-rpmsg" 22 23Optional properties (SPI): 24- google,cros-ec-spi-pre-delay: Some implementations of the EC need a little 25 time to wake up from sleep before they can receive SPI transfers at a high 26 clock rate. This property specifies the delay, in usecs, between the 27 assertion of the CS to the start of the first clock pulse. 28- google,cros-ec-spi-msg-delay: Some implementations of the EC require some 29 additional processing time in order to accept new transactions. If the delay 30 between transactions is not long enough the EC may not be able to respond 31 properly to subsequent transactions and cause them to hang. This property 32 specifies the delay, in usecs, introduced between transactions to account 33 for the time required by the EC to get back into a state in which new data 34 can be accepted. 35 36Required properties (LPC): 37- compatible: "google,cros-ec-lpc" 38- reg: List of (IO address, size) pairs defining the interface uses 39 40Optional properties (all): 41- google,has-vbc-nvram: Some implementations of the EC include a small 42 nvram space used to store verified boot context data. This boolean flag 43 is used to specify whether this nvram is present or not. 44 45Example for I2C: 46 47i2c@12ca0000 { 48 cros-ec@1e { 49 reg = <0x1e>; 50 compatible = "google,cros-ec-i2c"; 51 interrupts = <14 0>; 52 interrupt-parent = <&wakeup_eint>; 53 wakeup-source; 54 }; 55 56 57Example for SPI: 58 59spi@131b0000 { 60 ec@0 { 61 compatible = "google,cros-ec-spi"; 62 reg = <0x0>; 63 interrupts = <14 0>; 64 interrupt-parent = <&wakeup_eint>; 65 wakeup-source; 66 spi-max-frequency = <5000000>; 67 controller-data { 68 cs-gpio = <&gpf0 3 4 3 0>; 69 samsung,spi-cs; 70 samsung,spi-feedback-delay = <2>; 71 }; 72 }; 73}; 74 75 76Example for LPC is not supplied as it is not yet implemented. 77