1====================================================================== 2Device tree bindings for the Aspeed Low Pin Count (LPC) Bus Controller 3====================================================================== 4 5The LPC bus is a means to bridge a host CPU to a number of low-bandwidth 6peripheral devices, replacing the use of the ISA bus in the age of PCI[0]. The 7primary use case of the Aspeed LPC controller is as a slave on the bus 8(typically in a Baseboard Management Controller SoC), but under certain 9conditions it can also take the role of bus master. 10 11The LPC controller is represented as a multi-function device to account for the 12mix of functionality, which includes, but is not limited to: 13 14* An IPMI Block Transfer[2] Controller 15 16* An LPC Host Controller: Manages LPC functions such as host vs slave mode, the 17 physical properties of some LPC pins, configuration of serial IRQs, and 18 APB-to-LPC bridging amonst other functions. 19 20* An LPC Host Interface Controller: Manages functions exposed to the host such 21 as LPC firmware hub cycles, configuration of the LPC-to-AHB mapping, UART 22 management and bus snoop configuration. 23 24* A set of SuperIO[3] scratch registers: Enables implementation of e.g. custom 25 hardware management protocols for handover between the host and baseboard 26 management controller. 27 28Additionally the state of the LPC controller influences the pinmux 29configuration, therefore the host portion of the controller is exposed as a 30syscon as a means to arbitrate access. 31 32[0] http://www.intel.com/design/chipsets/industry/25128901.pdf 33[1] https://www.renesas.com/en-sg/doc/products/mpumcu/001/rej09b0078_h8s2168.pdf?key=7c88837454702128622bee53acbda8f4 34[2] https://www.intel.com/content/dam/www/public/us/en/documents/product-briefs/ipmi-second-gen-interface-spec-v2-rev1-1.pdf 35[3] https://en.wikipedia.org/wiki/Super_I/O 36 37Required properties 38=================== 39 40- compatible: One of: 41 "aspeed,ast2400-lpc-v2", "simple-mfd", "syscon" 42 "aspeed,ast2500-lpc-v2", "simple-mfd", "syscon" 43 "aspeed,ast2600-lpc-v2", "simple-mfd", "syscon" 44 45- reg: contains the physical address and length values of the Aspeed 46 LPC memory region. 47 48- #address-cells: <1> 49- #size-cells: <1> 50- ranges: Maps 0 to the physical address and length of the LPC memory 51 region 52 53Example: 54 55lpc: lpc@1e789000 { 56 compatible = "aspeed,ast2500-lpc-v2", "simple-mfd", "syscon"; 57 reg = <0x1e789000 0x1000>; 58 59 #address-cells = <1>; 60 #size-cells = <1>; 61 ranges = <0x0 0x1e789000 0x1000>; 62 63 lpc_snoop: lpc-snoop@0 { 64 compatible = "aspeed,ast2600-lpc-snoop"; 65 reg = <0x0 0x80>; 66 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>; 67 snoop-ports = <0x80>; 68 }; 69}; 70 71 72LPC Host Interface Controller 73------------------- 74 75The LPC Host Interface Controller manages functions exposed to the host such as 76LPC firmware hub cycles, configuration of the LPC-to-AHB mapping, UART 77management and bus snoop configuration. 78 79Required properties: 80 81- compatible: One of: 82 "aspeed,ast2400-lpc-ctrl"; 83 "aspeed,ast2500-lpc-ctrl"; 84 "aspeed,ast2600-lpc-ctrl"; 85 86- reg: contains offset/length values of the host interface controller 87 memory regions 88 89- clocks: contains a phandle to the syscon node describing the clocks. 90 There should then be one cell representing the clock to use 91 92Optional properties: 93 94- memory-region: A phandle to a reserved_memory region to be used for the LPC 95 to AHB mapping 96 97- flash: A phandle to the SPI flash controller containing the flash to 98 be exposed over the LPC to AHB mapping 99 100Example: 101 102lpc_ctrl: lpc-ctrl@80 { 103 compatible = "aspeed,ast2500-lpc-ctrl"; 104 reg = <0x80 0x80>; 105 clocks = <&syscon ASPEED_CLK_GATE_LCLK>; 106 memory-region = <&flash_memory>; 107 flash = <&spi>; 108}; 109 110LPC Host Controller 111------------------- 112 113The Aspeed LPC Host Controller configures the Low Pin Count (LPC) bus behaviour 114between the host and the baseboard management controller. The registers exist 115in the "host" portion of the Aspeed LPC controller, which must be the parent of 116the LPC host controller node. 117 118Required properties: 119 120- compatible: One of: 121 "aspeed,ast2400-lhc"; 122 "aspeed,ast2500-lhc"; 123 "aspeed,ast2600-lhc"; 124 125- reg: contains offset/length values of the LHC memory regions. In the 126 AST2400 and AST2500 there are two regions. 127 128Example: 129 130lhc: lhc@a0 { 131 compatible = "aspeed,ast2500-lhc"; 132 reg = <0xa0 0x24 0xc8 0x8>; 133}; 134 135LPC reset control 136----------------- 137 138The UARTs present in the ASPEED SoC can have their resets tied to the reset 139state of the LPC bus. Some systems may chose to modify this configuration. 140 141Required properties: 142 143 - compatible: One of: 144 "aspeed,ast2600-lpc-reset"; 145 "aspeed,ast2500-lpc-reset"; 146 "aspeed,ast2400-lpc-reset"; 147 148 - reg: offset and length of the IP in the LHC memory region 149 - #reset-controller indicates the number of reset cells expected 150 151Example: 152 153lpc_reset: reset-controller@98 { 154 compatible = "aspeed,ast2500-lpc-reset"; 155 reg = <0x98 0x4>; 156 #reset-cells = <1>; 157}; 158