1# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/memory-controllers/xlnx,zynq-ddrc-a05.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: Zynq A05 DDR Memory Controller 8 9maintainers: 10 - Krzysztof Kozlowski <krzk@kernel.org> 11 - Manish Narani <manish.narani@xilinx.com> 12 - Michal Simek <michal.simek@xilinx.com> 13 14description: 15 The Zynq DDR ECC controller has an optional ECC support in half-bus width 16 (16-bit) configuration. It is cappable of correcting single bit ECC errors 17 and detecting double bit ECC errors. 18 19properties: 20 compatible: 21 const: xlnx,zynq-ddrc-a05 22 23 reg: 24 maxItems: 1 25 26required: 27 - compatible 28 - reg 29 30additionalProperties: false 31 32examples: 33 - | 34 memory-controller@f8006000 { 35 compatible = "xlnx,zynq-ddrc-a05"; 36 reg = <0xf8006000 0x1000>; 37 }; 38... 39