1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/memory-controllers/st,stm32-fmc2-ebi.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: STMicroelectronics Flexible Memory Controller 2 (FMC2) Bindings 8 9description: | 10 The FMC2 functional block makes the interface with: synchronous and 11 asynchronous static devices (such as PSNOR, PSRAM or other memory-mapped 12 peripherals) and NAND flash memories. 13 Its main purposes are: 14 - to translate AXI transactions into the appropriate external device 15 protocol 16 - to meet the access time requirements of the external devices 17 All external devices share the addresses, data and control signals with the 18 controller. Each external device is accessed by means of a unique Chip 19 Select. The FMC2 performs only one access at a time to an external device. 20 21maintainers: 22 - Christophe Kerello <christophe.kerello@st.com> 23 24properties: 25 compatible: 26 const: st,stm32mp1-fmc2-ebi 27 28 reg: 29 maxItems: 1 30 31 clocks: 32 maxItems: 1 33 34 resets: 35 maxItems: 1 36 37 "#address-cells": 38 const: 2 39 40 "#size-cells": 41 const: 1 42 43 ranges: 44 description: | 45 Reflects the memory layout with four integer values per bank. Format: 46 <bank-number> 0 <address of the bank> <size> 47 48patternProperties: 49 "^.*@[0-4],[a-f0-9]+$": 50 type: object 51 52 properties: 53 reg: 54 description: Bank number, base address and size of the device. 55 56 st,fmc2-ebi-cs-transaction-type: 57 description: | 58 Select one of the transactions type supported 59 0: Asynchronous mode 1 SRAM/FRAM. 60 1: Asynchronous mode 1 PSRAM. 61 2: Asynchronous mode A SRAM/FRAM. 62 3: Asynchronous mode A PSRAM. 63 4: Asynchronous mode 2 NOR. 64 5: Asynchronous mode B NOR. 65 6: Asynchronous mode C NOR. 66 7: Asynchronous mode D NOR. 67 8: Synchronous read synchronous write PSRAM. 68 9: Synchronous read asynchronous write PSRAM. 69 10: Synchronous read synchronous write NOR. 70 11: Synchronous read asynchronous write NOR. 71 $ref: /schemas/types.yaml#/definitions/uint32 72 minimum: 0 73 maximum: 11 74 75 st,fmc2-ebi-cs-cclk-enable: 76 description: Continuous clock enable (first bank must be configured 77 in synchronous mode). The FMC_CLK is generated continuously 78 during asynchronous and synchronous access. By default, the 79 FMC_CLK is only generated during synchronous access. 80 $ref: /schemas/types.yaml#/definitions/flag 81 82 st,fmc2-ebi-cs-mux-enable: 83 description: Address/Data multiplexed on databus (valid only with 84 NOR and PSRAM transactions type). By default, Address/Data 85 are not multiplexed. 86 $ref: /schemas/types.yaml#/definitions/flag 87 88 st,fmc2-ebi-cs-buswidth: 89 description: Data bus width 90 $ref: /schemas/types.yaml#/definitions/uint32 91 enum: [ 8, 16 ] 92 default: 16 93 94 st,fmc2-ebi-cs-waitpol-high: 95 description: Wait signal polarity (NWAIT signal active high). 96 By default, NWAIT is active low. 97 $ref: /schemas/types.yaml#/definitions/flag 98 99 st,fmc2-ebi-cs-waitcfg-enable: 100 description: The NWAIT signal indicates wheither the data from the 101 device are valid or if a wait state must be inserted when accessing 102 the device in synchronous mode. By default, the NWAIT signal is 103 active one data cycle before wait state. 104 $ref: /schemas/types.yaml#/definitions/flag 105 106 st,fmc2-ebi-cs-wait-enable: 107 description: The NWAIT signal is enabled (its level is taken into 108 account after the programmed latency period to insert wait states 109 if asserted). By default, the NWAIT signal is disabled. 110 $ref: /schemas/types.yaml#/definitions/flag 111 112 st,fmc2-ebi-cs-asyncwait-enable: 113 description: The NWAIT signal is taken into account during asynchronous 114 transactions. By default, the NWAIT signal is not taken into account 115 during asynchronous transactions. 116 $ref: /schemas/types.yaml#/definitions/flag 117 118 st,fmc2-ebi-cs-cpsize: 119 description: CRAM page size. The controller splits the burst access 120 when the memory page is reached. By default, no burst split when 121 crossing page boundary. 122 $ref: /schemas/types.yaml#/definitions/uint32 123 enum: [ 0, 128, 256, 512, 1024 ] 124 default: 0 125 126 st,fmc2-ebi-cs-byte-lane-setup-ns: 127 description: This property configures the byte lane setup timing 128 defined in nanoseconds from NBLx low to Chip Select NEx low. 129 130 st,fmc2-ebi-cs-address-setup-ns: 131 description: This property defines the duration of the address setup 132 phase in nanoseconds used for asynchronous read/write transactions. 133 134 st,fmc2-ebi-cs-address-hold-ns: 135 description: This property defines the duration of the address hold 136 phase in nanoseconds used for asynchronous multiplexed read/write 137 transactions. 138 139 st,fmc2-ebi-cs-data-setup-ns: 140 description: This property defines the duration of the data setup phase 141 in nanoseconds used for asynchronous read/write transactions. 142 143 st,fmc2-ebi-cs-bus-turnaround-ns: 144 description: This property defines the delay in nanoseconds between the 145 end of current read/write transaction and the next transaction. 146 147 st,fmc2-ebi-cs-data-hold-ns: 148 description: This property defines the duration of the data hold phase 149 in nanoseconds used for asynchronous read/write transactions. 150 151 st,fmc2-ebi-cs-clk-period-ns: 152 description: This property defines the FMC_CLK output signal period in 153 nanoseconds. 154 155 st,fmc2-ebi-cs-data-latency-ns: 156 description: This property defines the data latency before reading or 157 writing the first data in nanoseconds. 158 159 st,fmc2_ebi-cs-write-address-setup-ns: 160 description: This property defines the duration of the address setup 161 phase in nanoseconds used for asynchronous write transactions. 162 163 st,fmc2-ebi-cs-write-address-hold-ns: 164 description: This property defines the duration of the address hold 165 phase in nanoseconds used for asynchronous multiplexed write 166 transactions. 167 168 st,fmc2-ebi-cs-write-data-setup-ns: 169 description: This property defines the duration of the data setup 170 phase in nanoseconds used for asynchronous write transactions. 171 172 st,fmc2-ebi-cs-write-bus-turnaround-ns: 173 description: This property defines the delay between the end of current 174 write transaction and the next transaction in nanoseconds. 175 176 st,fmc2-ebi-cs-write-data-hold-ns: 177 description: This property defines the duration of the data hold phase 178 in nanoseconds used for asynchronous write transactions. 179 180 st,fmc2-ebi-cs-max-low-pulse-ns: 181 description: This property defines the maximum chip select low pulse 182 duration in nanoseconds for synchronous transactions. When this timing 183 reaches 0, the controller splits the current access, toggles NE to 184 allow device refresh and restarts a new access. 185 186 required: 187 - reg 188 189required: 190 - "#address-cells" 191 - "#size-cells" 192 - compatible 193 - reg 194 - clocks 195 - ranges 196 197examples: 198 - | 199 #include <dt-bindings/interrupt-controller/arm-gic.h> 200 #include <dt-bindings/clock/stm32mp1-clks.h> 201 #include <dt-bindings/reset/stm32mp1-resets.h> 202 memory-controller@58002000 { 203 #address-cells = <2>; 204 #size-cells = <1>; 205 compatible = "st,stm32mp1-fmc2-ebi"; 206 reg = <0x58002000 0x1000>; 207 clocks = <&rcc FMC_K>; 208 resets = <&rcc FMC_R>; 209 210 ranges = <0 0 0x60000000 0x04000000>, /* EBI CS 1 */ 211 <1 0 0x64000000 0x04000000>, /* EBI CS 2 */ 212 <2 0 0x68000000 0x04000000>, /* EBI CS 3 */ 213 <3 0 0x6c000000 0x04000000>, /* EBI CS 4 */ 214 <4 0 0x80000000 0x10000000>; /* NAND */ 215 216 psram@0,0 { 217 compatible = "mtd-ram"; 218 reg = <0 0x00000000 0x100000>; 219 bank-width = <2>; 220 221 st,fmc2-ebi-cs-transaction-type = <1>; 222 st,fmc2-ebi-cs-address-setup-ns = <60>; 223 st,fmc2-ebi-cs-data-setup-ns = <30>; 224 st,fmc2-ebi-cs-bus-turnaround-ns = <5>; 225 }; 226 227 nand-controller@4,0 { 228 #address-cells = <1>; 229 #size-cells = <0>; 230 compatible = "st,stm32mp1-fmc2-nfc"; 231 reg = <4 0x00000000 0x1000>, 232 <4 0x08010000 0x1000>, 233 <4 0x08020000 0x1000>, 234 <4 0x01000000 0x1000>, 235 <4 0x09010000 0x1000>, 236 <4 0x09020000 0x1000>; 237 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; 238 dmas = <&mdma1 20 0x2 0x12000a02 0x0 0x0>, 239 <&mdma1 20 0x2 0x12000a08 0x0 0x0>, 240 <&mdma1 21 0x2 0x12000a0a 0x0 0x0>; 241 dma-names = "tx", "rx", "ecc"; 242 243 nand@0 { 244 reg = <0>; 245 nand-on-flash-bbt; 246 #address-cells = <1>; 247 #size-cells = <1>; 248 }; 249 }; 250 }; 251 252... 253