1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/memory-controllers/nvidia,tegra20-mc.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: NVIDIA Tegra20 SoC Memory Controller 8 9maintainers: 10 - Dmitry Osipenko <digetx@gmail.com> 11 - Jon Hunter <jonathanh@nvidia.com> 12 - Thierry Reding <thierry.reding@gmail.com> 13 14description: | 15 The Tegra20 Memory Controller merges request streams from various client 16 interfaces into request stream(s) for the various memory target devices, 17 and returns response data to the various clients. The Memory Controller 18 has a configurable arbitration algorithm to allow the user to fine-tune 19 performance among the various clients. 20 21 Tegra20 Memory Controller includes the GART (Graphics Address Relocation 22 Table) which allows Memory Controller to provide a linear view of a 23 fragmented memory pages. 24 25properties: 26 compatible: 27 const: nvidia,tegra20-mc-gart 28 29 reg: 30 items: 31 - description: controller registers 32 - description: GART registers 33 34 clocks: 35 maxItems: 1 36 37 clock-names: 38 items: 39 - const: mc 40 41 interrupts: 42 maxItems: 1 43 44 "#reset-cells": 45 const: 1 46 47 "#iommu-cells": 48 const: 0 49 50 "#interconnect-cells": 51 const: 1 52 53required: 54 - compatible 55 - reg 56 - interrupts 57 - clocks 58 - clock-names 59 - "#reset-cells" 60 - "#iommu-cells" 61 - "#interconnect-cells" 62 63additionalProperties: false 64 65examples: 66 - | 67 memory-controller@7000f000 { 68 compatible = "nvidia,tegra20-mc-gart"; 69 reg = <0x7000f000 0x400>, /* Controller registers */ 70 <0x58000000 0x02000000>; /* GART aperture */ 71 clocks = <&clock_controller 32>; 72 clock-names = "mc"; 73 74 interrupts = <0 77 4>; 75 76 #iommu-cells = <0>; 77 #reset-cells = <1>; 78 #interconnect-cells = <1>; 79 }; 80