1Embedded Memory Controller 2 3Properties: 4- name : Should be emc 5- #address-cells : Should be 1 6- #size-cells : Should be 0 7- compatible : Should contain "nvidia,tegra20-emc". 8- reg : Offset and length of the register set for the device 9- nvidia,use-ram-code : If present, the sub-nodes will be addressed 10 and chosen using the ramcode board selector. If omitted, only one 11 set of tables can be present and said tables will be used 12 irrespective of ram-code configuration. 13- interrupts : Should contain EMC General interrupt. 14- clocks : Should contain EMC clock. 15 16Child device nodes describe the memory settings for different configurations and clock rates. 17 18Example: 19 20 memory-controller@7000f400 { 21 #address-cells = < 1 >; 22 #size-cells = < 0 >; 23 compatible = "nvidia,tegra20-emc"; 24 reg = <0x7000f4000 0x200>; 25 interrupts = <0 78 0x04>; 26 clocks = <&tegra_car TEGRA20_CLK_EMC>; 27 } 28 29 30Embedded Memory Controller ram-code table 31 32If the emc node has the nvidia,use-ram-code property present, then the 33next level of nodes below the emc table are used to specify which settings 34apply for which ram-code settings. 35 36If the emc node lacks the nvidia,use-ram-code property, this level is omitted 37and the tables are stored directly under the emc node (see below). 38 39Properties: 40 41- name : Should be emc-tables 42- nvidia,ram-code : the binary representation of the ram-code board strappings 43 for which this node (and children) are valid. 44 45 46 47Embedded Memory Controller configuration table 48 49This is a table containing the EMC register settings for the various 50operating speeds of the memory controller. They are always located as 51subnodes of the emc controller node. 52 53There are two ways of specifying which tables to use: 54 55* The simplest is if there is just one set of tables in the device tree, 56 and they will always be used (based on which frequency is used). 57 This is the preferred method, especially when firmware can fill in 58 this information based on the specific system information and just 59 pass it on to the kernel. 60 61* The slightly more complex one is when more than one memory configuration 62 might exist on the system. The Tegra20 platform handles this during 63 early boot by selecting one out of possible 4 memory settings based 64 on a 2-pin "ram code" bootstrap setting on the board. The values of 65 these strappings can be read through a register in the SoC, and thus 66 used to select which tables to use. 67 68Properties: 69- name : Should be emc-table 70- compatible : Should contain "nvidia,tegra20-emc-table". 71- reg : either an opaque enumerator to tell different tables apart, or 72 the valid frequency for which the table should be used (in kHz). 73- clock-frequency : the clock frequency for the EMC at which this 74 table should be used (in kHz). 75- nvidia,emc-registers : a 46 word array of EMC registers to be programmed 76 for operation at the 'clock-frequency' setting. 77 The order and contents of the registers are: 78 RC, RFC, RAS, RP, R2W, W2R, R2P, W2P, RD_RCD, WR_RCD, RRD, REXT, 79 WDV, QUSE, QRST, QSAFE, RDV, REFRESH, BURST_REFRESH_NUM, PDEX2WR, 80 PDEX2RD, PCHG2PDEN, ACT2PDEN, AR2PDEN, RW2PDEN, TXSR, TCKE, TFAW, 81 TRPAB, TCLKSTABLE, TCLKSTOP, TREFBW, QUSE_EXTRA, FBIO_CFG6, ODT_WRITE, 82 ODT_READ, FBIO_CFG5, CFG_DIG_DLL, DLL_XFORM_DQS, DLL_XFORM_QUSE, 83 ZCAL_REF_CNT, ZCAL_WAIT_CNT, AUTO_CAL_INTERVAL, CFG_CLKTRIM_0, 84 CFG_CLKTRIM_1, CFG_CLKTRIM_2 85 86 emc-table@166000 { 87 reg = <166000>; 88 compatible = "nvidia,tegra20-emc-table"; 89 clock-frequency = < 166000 >; 90 nvidia,emc-registers = < 0 0 0 0 0 0 0 0 0 0 0 0 0 0 91 0 0 0 0 0 0 0 0 0 0 0 0 0 0 92 0 0 0 0 0 0 0 0 0 0 0 0 0 0 93 0 0 0 0 >; 94 }; 95 96 emc-table@333000 { 97 reg = <333000>; 98 compatible = "nvidia,tegra20-emc-table"; 99 clock-frequency = < 333000 >; 100 nvidia,emc-registers = < 0 0 0 0 0 0 0 0 0 0 0 0 0 0 101 0 0 0 0 0 0 0 0 0 0 0 0 0 0 102 0 0 0 0 0 0 0 0 0 0 0 0 0 0 103 0 0 0 0 >; 104 }; 105