1Embedded Memory Controller 2 3Properties: 4- name : Should be emc 5- #address-cells : Should be 1 6- #size-cells : Should be 0 7- compatible : Should contain "nvidia,tegra20-emc". 8- reg : Offset and length of the register set for the device 9- nvidia,use-ram-code : If present, the sub-nodes will be addressed 10 and chosen using the ramcode board selector. If omitted, only one 11 set of tables can be present and said tables will be used 12 irrespective of ram-code configuration. 13- interrupts : Should contain EMC General interrupt. 14- clocks : Should contain EMC clock. 15- nvidia,memory-controller : Phandle of the Memory Controller node. 16- #interconnect-cells : Should be 0. 17- operating-points-v2: See ../bindings/opp/opp.txt for details. 18 19For each opp entry in 'operating-points-v2' table: 20- opp-supported-hw: One bitfield indicating SoC process ID mask 21 22 A bitwise AND is performed against this value and if any bit 23 matches, the OPP gets enabled. 24 25Optional properties: 26- power-domains: Phandle of the SoC "core" power domain. 27 28Child device nodes describe the memory settings for different configurations and clock rates. 29 30Example: 31 32 opp_table: opp-table { 33 compatible = "operating-points-v2"; 34 35 opp@36000000 { 36 opp-microvolt = <950000 950000 1300000>; 37 opp-hz = /bits/ 64 <36000000>; 38 }; 39 ... 40 }; 41 42 memory-controller@7000f400 { 43 #address-cells = < 1 >; 44 #size-cells = < 0 >; 45 #interconnect-cells = <0>; 46 compatible = "nvidia,tegra20-emc"; 47 reg = <0x7000f400 0x400>; 48 interrupts = <0 78 0x04>; 49 clocks = <&tegra_car TEGRA20_CLK_EMC>; 50 nvidia,memory-controller = <&mc>; 51 power-domains = <&domain>; 52 operating-points-v2 = <&opp_table>; 53 } 54 55 56Embedded Memory Controller ram-code table 57 58If the emc node has the nvidia,use-ram-code property present, then the 59next level of nodes below the emc table are used to specify which settings 60apply for which ram-code settings. 61 62If the emc node lacks the nvidia,use-ram-code property, this level is omitted 63and the tables are stored directly under the emc node (see below). 64 65Properties: 66 67- name : Should be emc-tables 68- nvidia,ram-code : the binary representation of the ram-code board strappings 69 for which this node (and children) are valid. 70 71 72 73Embedded Memory Controller configuration table 74 75This is a table containing the EMC register settings for the various 76operating speeds of the memory controller. They are always located as 77subnodes of the emc controller node. 78 79There are two ways of specifying which tables to use: 80 81* The simplest is if there is just one set of tables in the device tree, 82 and they will always be used (based on which frequency is used). 83 This is the preferred method, especially when firmware can fill in 84 this information based on the specific system information and just 85 pass it on to the kernel. 86 87* The slightly more complex one is when more than one memory configuration 88 might exist on the system. The Tegra20 platform handles this during 89 early boot by selecting one out of possible 4 memory settings based 90 on a 2-pin "ram code" bootstrap setting on the board. The values of 91 these strappings can be read through a register in the SoC, and thus 92 used to select which tables to use. 93 94Properties: 95- name : Should be emc-table 96- compatible : Should contain "nvidia,tegra20-emc-table". 97- reg : either an opaque enumerator to tell different tables apart, or 98 the valid frequency for which the table should be used (in kHz). 99- clock-frequency : the clock frequency for the EMC at which this 100 table should be used (in kHz). 101- nvidia,emc-registers : a 46 word array of EMC registers to be programmed 102 for operation at the 'clock-frequency' setting. 103 The order and contents of the registers are: 104 RC, RFC, RAS, RP, R2W, W2R, R2P, W2P, RD_RCD, WR_RCD, RRD, REXT, 105 WDV, QUSE, QRST, QSAFE, RDV, REFRESH, BURST_REFRESH_NUM, PDEX2WR, 106 PDEX2RD, PCHG2PDEN, ACT2PDEN, AR2PDEN, RW2PDEN, TXSR, TCKE, TFAW, 107 TRPAB, TCLKSTABLE, TCLKSTOP, TREFBW, QUSE_EXTRA, FBIO_CFG6, ODT_WRITE, 108 ODT_READ, FBIO_CFG5, CFG_DIG_DLL, DLL_XFORM_DQS, DLL_XFORM_QUSE, 109 ZCAL_REF_CNT, ZCAL_WAIT_CNT, AUTO_CAL_INTERVAL, CFG_CLKTRIM_0, 110 CFG_CLKTRIM_1, CFG_CLKTRIM_2 111 112 emc-table@166000 { 113 reg = <166000>; 114 compatible = "nvidia,tegra20-emc-table"; 115 clock-frequency = < 166000 >; 116 nvidia,emc-registers = < 0 0 0 0 0 0 0 0 0 0 0 0 0 0 117 0 0 0 0 0 0 0 0 0 0 0 0 0 0 118 0 0 0 0 0 0 0 0 0 0 0 0 0 0 119 0 0 0 0 >; 120 }; 121 122 emc-table@333000 { 123 reg = <333000>; 124 compatible = "nvidia,tegra20-emc-table"; 125 clock-frequency = < 333000 >; 126 nvidia,emc-registers = < 0 0 0 0 0 0 0 0 0 0 0 0 0 0 127 0 0 0 0 0 0 0 0 0 0 0 0 0 0 128 0 0 0 0 0 0 0 0 0 0 0 0 0 0 129 0 0 0 0 >; 130 }; 131