1# SPDX-License-Identifier: (GPL-2.0) 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/memory-controllers/nvidia,tegra124-mc.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: NVIDIA Tegra124 SoC Memory Controller 8 9maintainers: 10 - Jon Hunter <jonathanh@nvidia.com> 11 - Thierry Reding <thierry.reding@gmail.com> 12 13description: | 14 Tegra124 SoC features a hybrid 2x32-bit / 1x64-bit memory controller. 15 These are interleaved to provide high performance with the load shared across 16 two memory channels. The Tegra124 Memory Controller handles memory requests 17 from internal clients and arbitrates among them to allocate memory bandwidth 18 for DDR3L and LPDDR3 SDRAMs. 19 20properties: 21 compatible: 22 const: nvidia,tegra124-mc 23 24 reg: 25 maxItems: 1 26 27 clocks: 28 maxItems: 1 29 30 clock-names: 31 items: 32 - const: mc 33 34 interrupts: 35 maxItems: 1 36 37 "#reset-cells": 38 const: 1 39 40 "#iommu-cells": 41 const: 1 42 43patternProperties: 44 "^emc-timings-[0-9]+$": 45 type: object 46 properties: 47 nvidia,ram-code: 48 $ref: /schemas/types.yaml#/definitions/uint32 49 description: 50 Value of RAM_CODE this timing set is used for. 51 52 patternProperties: 53 "^timing-[0-9]+$": 54 type: object 55 properties: 56 clock-frequency: 57 description: 58 Memory clock rate in Hz. 59 minimum: 1000000 60 maximum: 1066000000 61 62 nvidia,emem-configuration: 63 $ref: /schemas/types.yaml#/definitions/uint32-array 64 description: | 65 Values to be written to the EMEM register block. See section 66 "15.6.1 MC Registers" in the TRM. 67 items: 68 - description: MC_EMEM_ARB_CFG 69 - description: MC_EMEM_ARB_OUTSTANDING_REQ 70 - description: MC_EMEM_ARB_TIMING_RCD 71 - description: MC_EMEM_ARB_TIMING_RP 72 - description: MC_EMEM_ARB_TIMING_RC 73 - description: MC_EMEM_ARB_TIMING_RAS 74 - description: MC_EMEM_ARB_TIMING_FAW 75 - description: MC_EMEM_ARB_TIMING_RRD 76 - description: MC_EMEM_ARB_TIMING_RAP2PRE 77 - description: MC_EMEM_ARB_TIMING_WAP2PRE 78 - description: MC_EMEM_ARB_TIMING_R2R 79 - description: MC_EMEM_ARB_TIMING_W2W 80 - description: MC_EMEM_ARB_TIMING_R2W 81 - description: MC_EMEM_ARB_TIMING_W2R 82 - description: MC_EMEM_ARB_DA_TURNS 83 - description: MC_EMEM_ARB_DA_COVERS 84 - description: MC_EMEM_ARB_MISC0 85 - description: MC_EMEM_ARB_MISC1 86 - description: MC_EMEM_ARB_RING1_THROTTLE 87 88 required: 89 - clock-frequency 90 - nvidia,emem-configuration 91 92 additionalProperties: false 93 94 required: 95 - nvidia,ram-code 96 97 additionalProperties: false 98 99required: 100 - compatible 101 - reg 102 - interrupts 103 - clocks 104 - clock-names 105 - "#reset-cells" 106 - "#iommu-cells" 107 108additionalProperties: false 109 110examples: 111 - | 112 memory-controller@70019000 { 113 compatible = "nvidia,tegra124-mc"; 114 reg = <0x70019000 0x1000>; 115 clocks = <&tegra_car 32>; 116 clock-names = "mc"; 117 118 interrupts = <0 77 4>; 119 120 #iommu-cells = <1>; 121 #reset-cells = <1>; 122 123 emc-timings-3 { 124 nvidia,ram-code = <3>; 125 126 timing-12750000 { 127 clock-frequency = <12750000>; 128 129 nvidia,emem-configuration = < 130 0x40040001 /* MC_EMEM_ARB_CFG */ 131 0x8000000a /* MC_EMEM_ARB_OUTSTANDING_REQ */ 132 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */ 133 0x00000001 /* MC_EMEM_ARB_TIMING_RP */ 134 0x00000002 /* MC_EMEM_ARB_TIMING_RC */ 135 0x00000000 /* MC_EMEM_ARB_TIMING_RAS */ 136 0x00000002 /* MC_EMEM_ARB_TIMING_FAW */ 137 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */ 138 0x00000002 /* MC_EMEM_ARB_TIMING_RAP2PRE */ 139 0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */ 140 0x00000003 /* MC_EMEM_ARB_TIMING_R2R */ 141 0x00000002 /* MC_EMEM_ARB_TIMING_W2W */ 142 0x00000003 /* MC_EMEM_ARB_TIMING_R2W */ 143 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */ 144 0x06030203 /* MC_EMEM_ARB_DA_TURNS */ 145 0x000a0402 /* MC_EMEM_ARB_DA_COVERS */ 146 0x77e30303 /* MC_EMEM_ARB_MISC0 */ 147 0x70000f03 /* MC_EMEM_ARB_MISC1 */ 148 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ 149 >; 150 }; 151 }; 152 }; 153