1# SPDX-License-Identifier: (GPL-2.0) 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/memory-controllers/nvidia,tegra30-emc.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: NVIDIA Tegra30 SoC External Memory Controller 8 9maintainers: 10 - Dmitry Osipenko <digetx@gmail.com> 11 - Jon Hunter <jonathanh@nvidia.com> 12 - Thierry Reding <thierry.reding@gmail.com> 13 14description: | 15 The EMC interfaces with the off-chip SDRAM to service the request stream 16 sent from Memory Controller. The EMC also has various performance-affecting 17 settings beyond the obvious SDRAM configuration parameters and initialization 18 settings. Tegra30 EMC supports multiple JEDEC standard protocols: LPDDR2, 19 LPDDR3, and DDR3. 20 21properties: 22 compatible: 23 const: nvidia,tegra30-emc 24 25 reg: 26 maxItems: 1 27 28 clocks: 29 maxItems: 1 30 31 interrupts: 32 maxItems: 1 33 34 "#interconnect-cells": 35 const: 0 36 37 nvidia,memory-controller: 38 $ref: /schemas/types.yaml#/definitions/phandle 39 description: 40 Phandle of the Memory Controller node. 41 42 core-supply: 43 description: 44 Phandle of voltage regulator of the SoC "core" power domain. 45 46 operating-points-v2: 47 description: 48 Should contain freqs and voltages and opp-supported-hw property, which 49 is a bitfield indicating SoC speedo ID mask. 50 51patternProperties: 52 "^emc-timings-[0-9]+$": 53 type: object 54 properties: 55 nvidia,ram-code: 56 $ref: /schemas/types.yaml#/definitions/uint32 57 description: 58 Value of RAM_CODE this timing set is used for. 59 60 patternProperties: 61 "^timing-[0-9]+$": 62 type: object 63 properties: 64 clock-frequency: 65 description: 66 Memory clock rate in Hz. 67 minimum: 1000000 68 maximum: 900000000 69 70 nvidia,emc-auto-cal-interval: 71 description: 72 Pad calibration interval in microseconds. 73 $ref: /schemas/types.yaml#/definitions/uint32 74 minimum: 0 75 maximum: 2097151 76 77 nvidia,emc-mode-1: 78 $ref: /schemas/types.yaml#/definitions/uint32 79 description: 80 Mode Register 1. 81 82 nvidia,emc-mode-2: 83 $ref: /schemas/types.yaml#/definitions/uint32 84 description: 85 Mode Register 2. 86 87 nvidia,emc-mode-reset: 88 $ref: /schemas/types.yaml#/definitions/uint32 89 description: 90 Mode Register 0. 91 92 nvidia,emc-zcal-cnt-long: 93 description: 94 Number of EMC clocks to wait before issuing any commands after 95 sending ZCAL_MRW_CMD. 96 $ref: /schemas/types.yaml#/definitions/uint32 97 minimum: 0 98 maximum: 1023 99 100 nvidia,emc-cfg-dyn-self-ref: 101 type: boolean 102 description: 103 Dynamic self-refresh enabled. 104 105 nvidia,emc-cfg-periodic-qrst: 106 type: boolean 107 description: 108 FBIO "read" FIFO periodic resetting enabled. 109 110 nvidia,emc-configuration: 111 description: 112 EMC timing characterization data. These are the registers 113 (see section "18.13.2 EMC Registers" in the TRM) whose values 114 need to be specified, according to the board documentation. 115 $ref: /schemas/types.yaml#/definitions/uint32-array 116 items: 117 - description: EMC_RC 118 - description: EMC_RFC 119 - description: EMC_RAS 120 - description: EMC_RP 121 - description: EMC_R2W 122 - description: EMC_W2R 123 - description: EMC_R2P 124 - description: EMC_W2P 125 - description: EMC_RD_RCD 126 - description: EMC_WR_RCD 127 - description: EMC_RRD 128 - description: EMC_REXT 129 - description: EMC_WEXT 130 - description: EMC_WDV 131 - description: EMC_QUSE 132 - description: EMC_QRST 133 - description: EMC_QSAFE 134 - description: EMC_RDV 135 - description: EMC_REFRESH 136 - description: EMC_BURST_REFRESH_NUM 137 - description: EMC_PRE_REFRESH_REQ_CNT 138 - description: EMC_PDEX2WR 139 - description: EMC_PDEX2RD 140 - description: EMC_PCHG2PDEN 141 - description: EMC_ACT2PDEN 142 - description: EMC_AR2PDEN 143 - description: EMC_RW2PDEN 144 - description: EMC_TXSR 145 - description: EMC_TXSRDLL 146 - description: EMC_TCKE 147 - description: EMC_TFAW 148 - description: EMC_TRPAB 149 - description: EMC_TCLKSTABLE 150 - description: EMC_TCLKSTOP 151 - description: EMC_TREFBW 152 - description: EMC_QUSE_EXTRA 153 - description: EMC_FBIO_CFG6 154 - description: EMC_ODT_WRITE 155 - description: EMC_ODT_READ 156 - description: EMC_FBIO_CFG5 157 - description: EMC_CFG_DIG_DLL 158 - description: EMC_CFG_DIG_DLL_PERIOD 159 - description: EMC_DLL_XFORM_DQS0 160 - description: EMC_DLL_XFORM_DQS1 161 - description: EMC_DLL_XFORM_DQS2 162 - description: EMC_DLL_XFORM_DQS3 163 - description: EMC_DLL_XFORM_DQS4 164 - description: EMC_DLL_XFORM_DQS5 165 - description: EMC_DLL_XFORM_DQS6 166 - description: EMC_DLL_XFORM_DQS7 167 - description: EMC_DLL_XFORM_QUSE0 168 - description: EMC_DLL_XFORM_QUSE1 169 - description: EMC_DLL_XFORM_QUSE2 170 - description: EMC_DLL_XFORM_QUSE3 171 - description: EMC_DLL_XFORM_QUSE4 172 - description: EMC_DLL_XFORM_QUSE5 173 - description: EMC_DLL_XFORM_QUSE6 174 - description: EMC_DLL_XFORM_QUSE7 175 - description: EMC_DLI_TRIM_TXDQS0 176 - description: EMC_DLI_TRIM_TXDQS1 177 - description: EMC_DLI_TRIM_TXDQS2 178 - description: EMC_DLI_TRIM_TXDQS3 179 - description: EMC_DLI_TRIM_TXDQS4 180 - description: EMC_DLI_TRIM_TXDQS5 181 - description: EMC_DLI_TRIM_TXDQS6 182 - description: EMC_DLI_TRIM_TXDQS7 183 - description: EMC_DLL_XFORM_DQ0 184 - description: EMC_DLL_XFORM_DQ1 185 - description: EMC_DLL_XFORM_DQ2 186 - description: EMC_DLL_XFORM_DQ3 187 - description: EMC_XM2CMDPADCTRL 188 - description: EMC_XM2DQSPADCTRL2 189 - description: EMC_XM2DQPADCTRL2 190 - description: EMC_XM2CLKPADCTRL 191 - description: EMC_XM2COMPPADCTRL 192 - description: EMC_XM2VTTGENPADCTRL 193 - description: EMC_XM2VTTGENPADCTRL2 194 - description: EMC_XM2QUSEPADCTRL 195 - description: EMC_XM2DQSPADCTRL3 196 - description: EMC_CTT_TERM_CTRL 197 - description: EMC_ZCAL_INTERVAL 198 - description: EMC_ZCAL_WAIT_CNT 199 - description: EMC_MRS_WAIT_CNT 200 - description: EMC_AUTO_CAL_CONFIG 201 - description: EMC_CTT 202 - description: EMC_CTT_DURATION 203 - description: EMC_DYN_SELF_REF_CONTROL 204 - description: EMC_FBIO_SPARE 205 - description: EMC_CFG_RSV 206 207 required: 208 - clock-frequency 209 - nvidia,emc-auto-cal-interval 210 - nvidia,emc-mode-1 211 - nvidia,emc-mode-2 212 - nvidia,emc-mode-reset 213 - nvidia,emc-zcal-cnt-long 214 - nvidia,emc-configuration 215 216 additionalProperties: false 217 218 required: 219 - nvidia,ram-code 220 221 additionalProperties: false 222 223required: 224 - compatible 225 - reg 226 - interrupts 227 - clocks 228 - nvidia,memory-controller 229 - "#interconnect-cells" 230 - operating-points-v2 231 232additionalProperties: false 233 234examples: 235 - | 236 external-memory-controller@7000f400 { 237 compatible = "nvidia,tegra30-emc"; 238 reg = <0x7000f400 0x400>; 239 interrupts = <0 78 4>; 240 clocks = <&tegra_car 57>; 241 242 nvidia,memory-controller = <&mc>; 243 operating-points-v2 = <&dvfs_opp_table>; 244 core-supply = <&vdd_core>; 245 246 #interconnect-cells = <0>; 247 248 emc-timings-1 { 249 nvidia,ram-code = <1>; 250 251 timing-667000000 { 252 clock-frequency = <667000000>; 253 254 nvidia,emc-auto-cal-interval = <0x001fffff>; 255 nvidia,emc-mode-1 = <0x80100002>; 256 nvidia,emc-mode-2 = <0x80200018>; 257 nvidia,emc-mode-reset = <0x80000b71>; 258 nvidia,emc-zcal-cnt-long = <0x00000040>; 259 nvidia,emc-cfg-periodic-qrst; 260 261 nvidia,emc-configuration = < 262 0x00000020 /* EMC_RC */ 263 0x0000006a /* EMC_RFC */ 264 0x00000017 /* EMC_RAS */ 265 0x00000007 /* EMC_RP */ 266 0x00000005 /* EMC_R2W */ 267 0x0000000c /* EMC_W2R */ 268 0x00000003 /* EMC_R2P */ 269 0x00000011 /* EMC_W2P */ 270 0x00000007 /* EMC_RD_RCD */ 271 0x00000007 /* EMC_WR_RCD */ 272 0x00000002 /* EMC_RRD */ 273 0x00000001 /* EMC_REXT */ 274 0x00000000 /* EMC_WEXT */ 275 0x00000007 /* EMC_WDV */ 276 0x0000000a /* EMC_QUSE */ 277 0x00000009 /* EMC_QRST */ 278 0x0000000b /* EMC_QSAFE */ 279 0x00000011 /* EMC_RDV */ 280 0x00001412 /* EMC_REFRESH */ 281 0x00000000 /* EMC_BURST_REFRESH_NUM */ 282 0x00000504 /* EMC_PRE_REFRESH_REQ_CNT */ 283 0x00000002 /* EMC_PDEX2WR */ 284 0x0000000e /* EMC_PDEX2RD */ 285 0x00000001 /* EMC_PCHG2PDEN */ 286 0x00000000 /* EMC_ACT2PDEN */ 287 0x0000000c /* EMC_AR2PDEN */ 288 0x00000016 /* EMC_RW2PDEN */ 289 0x00000072 /* EMC_TXSR */ 290 0x00000200 /* EMC_TXSRDLL */ 291 0x00000005 /* EMC_TCKE */ 292 0x00000015 /* EMC_TFAW */ 293 0x00000000 /* EMC_TRPAB */ 294 0x00000006 /* EMC_TCLKSTABLE */ 295 0x00000007 /* EMC_TCLKSTOP */ 296 0x00001453 /* EMC_TREFBW */ 297 0x0000000b /* EMC_QUSE_EXTRA */ 298 0x00000006 /* EMC_FBIO_CFG6 */ 299 0x00000000 /* EMC_ODT_WRITE */ 300 0x00000000 /* EMC_ODT_READ */ 301 0x00005088 /* EMC_FBIO_CFG5 */ 302 0xf00b0191 /* EMC_CFG_DIG_DLL */ 303 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ 304 0x00000008 /* EMC_DLL_XFORM_DQS0 */ 305 0x00000008 /* EMC_DLL_XFORM_DQS1 */ 306 0x00000008 /* EMC_DLL_XFORM_DQS2 */ 307 0x00000008 /* EMC_DLL_XFORM_DQS3 */ 308 0x0000000a /* EMC_DLL_XFORM_DQS4 */ 309 0x0000000a /* EMC_DLL_XFORM_DQS5 */ 310 0x0000000a /* EMC_DLL_XFORM_DQS6 */ 311 0x0000000a /* EMC_DLL_XFORM_DQS7 */ 312 0x00018000 /* EMC_DLL_XFORM_QUSE0 */ 313 0x00018000 /* EMC_DLL_XFORM_QUSE1 */ 314 0x00018000 /* EMC_DLL_XFORM_QUSE2 */ 315 0x00018000 /* EMC_DLL_XFORM_QUSE3 */ 316 0x00000000 /* EMC_DLL_XFORM_QUSE4 */ 317 0x00000000 /* EMC_DLL_XFORM_QUSE5 */ 318 0x00000000 /* EMC_DLL_XFORM_QUSE6 */ 319 0x00000000 /* EMC_DLL_XFORM_QUSE7 */ 320 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */ 321 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */ 322 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */ 323 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */ 324 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */ 325 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */ 326 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */ 327 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */ 328 0x0000000a /* EMC_DLL_XFORM_DQ0 */ 329 0x0000000a /* EMC_DLL_XFORM_DQ1 */ 330 0x0000000a /* EMC_DLL_XFORM_DQ2 */ 331 0x0000000a /* EMC_DLL_XFORM_DQ3 */ 332 0x000002a0 /* EMC_XM2CMDPADCTRL */ 333 0x0800013d /* EMC_XM2DQSPADCTRL2 */ 334 0x22220000 /* EMC_XM2DQPADCTRL2 */ 335 0x77fff884 /* EMC_XM2CLKPADCTRL */ 336 0x01f1f501 /* EMC_XM2COMPPADCTRL */ 337 0x07077404 /* EMC_XM2VTTGENPADCTRL */ 338 0x54000000 /* EMC_XM2VTTGENPADCTRL2 */ 339 0x080001e8 /* EMC_XM2QUSEPADCTRL */ 340 0x0c000021 /* EMC_XM2DQSPADCTRL3 */ 341 0x00000802 /* EMC_CTT_TERM_CTRL */ 342 0x00020000 /* EMC_ZCAL_INTERVAL */ 343 0x00000100 /* EMC_ZCAL_WAIT_CNT */ 344 0x0155000c /* EMC_MRS_WAIT_CNT */ 345 0xa0f10000 /* EMC_AUTO_CAL_CONFIG */ 346 0x00000000 /* EMC_CTT */ 347 0x00000000 /* EMC_CTT_DURATION */ 348 0x800028a5 /* EMC_DYN_SELF_REF_CONTROL */ 349 0xe8000000 /* EMC_FBIO_SPARE */ 350 0xff00ff49 /* EMC_CFG_RSV */ 351 >; 352 }; 353 }; 354 }; 355