xref: /freebsd/sys/contrib/device-tree/Bindings/memory-controllers/mediatek,smi-common.yaml (revision d5b0e70f7e04d971691517ce1304d86a1e367e2e) 
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2# Copyright (c) 2020 MediaTek Inc.
3%YAML 1.2
4---
5$id: http://devicetree.org/schemas/memory-controllers/mediatek,smi-common.yaml#
6$schema: http://devicetree.org/meta-schemas/core.yaml#
7
8title: SMI (Smart Multimedia Interface) Common
9
10maintainers:
11  - Yong Wu <yong.wu@mediatek.com>
12
13description: |
14  The hardware block diagram please check bindings/iommu/mediatek,iommu.yaml
15
16  MediaTek SMI have two generations of HW architecture, here is the list
17  which generation the SoCs use:
18  generation 1: mt2701 and mt7623.
19  generation 2: mt2712, mt6779, mt8167, mt8173, mt8183, mt8186, mt8192 and mt8195.
20
21  There's slight differences between the two SMI, for generation 2, the
22  register which control the iommu port is at each larb's register base. But
23  for generation 1, the register is at smi ao base(smi always on register
24  base). Besides that, the smi async clock should be prepared and enabled for
25  SMI generation 1 to transform the smi clock into emi clock domain, but that is
26  not needed for SMI generation 2.
27
28properties:
29  compatible:
30    oneOf:
31      - enum:
32          - mediatek,mt2701-smi-common
33          - mediatek,mt2712-smi-common
34          - mediatek,mt6779-smi-common
35          - mediatek,mt8167-smi-common
36          - mediatek,mt8173-smi-common
37          - mediatek,mt8183-smi-common
38          - mediatek,mt8186-smi-common
39          - mediatek,mt8192-smi-common
40          - mediatek,mt8195-smi-common-vdo
41          - mediatek,mt8195-smi-common-vpp
42          - mediatek,mt8195-smi-sub-common
43
44      - description: for mt7623
45        items:
46          - const: mediatek,mt7623-smi-common
47          - const: mediatek,mt2701-smi-common
48
49  reg:
50    maxItems: 1
51
52  power-domains:
53    maxItems: 1
54
55  clocks:
56    description: |
57      apb and smi are mandatory. the async is only for generation 1 smi HW.
58      gals(global async local sync) also is optional, see below.
59    minItems: 2
60    items:
61      - description: apb is Advanced Peripheral Bus clock, It's the clock for
62          setting the register.
63      - description: smi is the clock for transfer data and command.
64      - description: Either asynchronous clock to help transform the smi clock
65          into the emi clock domain on Gen1 h/w, or the path0 clock of gals.
66      - description: gals1 is the path1 clock of gals.
67
68  clock-names:
69    minItems: 2
70    maxItems: 4
71
72  mediatek,smi:
73    $ref: /schemas/types.yaml#/definitions/phandle
74    description: a phandle to the smi-common node above. Only for sub-common.
75
76required:
77  - compatible
78  - reg
79  - power-domains
80  - clocks
81  - clock-names
82
83allOf:
84  - if:  # only for gen1 HW
85      properties:
86        compatible:
87          contains:
88            enum:
89              - mediatek,mt2701-smi-common
90    then:
91      properties:
92        clocks:
93          minItems: 3
94          maxItems: 3
95        clock-names:
96          items:
97            - const: apb
98            - const: smi
99            - const: async
100
101  - if:  # only for sub common
102      properties:
103        compatible:
104          contains:
105            enum:
106              - mediatek,mt8195-smi-sub-common
107    then:
108      required:
109        - mediatek,smi
110      properties:
111        clocks:
112          minItems: 3
113          maxItems: 3
114        clock-names:
115          items:
116            - const: apb
117            - const: smi
118            - const: gals0
119    else:
120      properties:
121        mediatek,smi: false
122
123  - if:  # for gen2 HW that have gals
124      properties:
125        compatible:
126          enum:
127            - mediatek,mt6779-smi-common
128            - mediatek,mt8183-smi-common
129            - mediatek,mt8186-smi-common
130            - mediatek,mt8192-smi-common
131            - mediatek,mt8195-smi-common-vdo
132            - mediatek,mt8195-smi-common-vpp
133
134    then:
135      properties:
136        clocks:
137          minItems: 4
138          maxItems: 4
139        clock-names:
140          items:
141            - const: apb
142            - const: smi
143            - const: gals0
144            - const: gals1
145
146    else:  # for gen2 HW that don't have gals
147      properties:
148        clocks:
149          minItems: 2
150          maxItems: 2
151        clock-names:
152          items:
153            - const: apb
154            - const: smi
155
156additionalProperties: false
157
158examples:
159  - |+
160    #include <dt-bindings/clock/mt8173-clk.h>
161    #include <dt-bindings/power/mt8173-power.h>
162
163    smi_common: smi@14022000 {
164            compatible = "mediatek,mt8173-smi-common";
165            reg = <0x14022000 0x1000>;
166            power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
167            clocks = <&mmsys CLK_MM_SMI_COMMON>,
168                     <&mmsys CLK_MM_SMI_COMMON>;
169            clock-names = "apb", "smi";
170    };
171