xref: /freebsd/sys/contrib/device-tree/Bindings/memory-controllers/mediatek,smi-common.yaml (revision 31ba4ce8898f9dfa5e7f054fdbc26e50a599a6e3) 
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2# Copyright (c) 2020 MediaTek Inc.
3%YAML 1.2
4---
5$id: http://devicetree.org/schemas/memory-controllers/mediatek,smi-common.yaml#
6$schema: http://devicetree.org/meta-schemas/core.yaml#
7
8title: SMI (Smart Multimedia Interface) Common
9
10maintainers:
11  - Yong Wu <yong.wu@mediatek.com>
12
13description: |
14  The hardware block diagram please check bindings/iommu/mediatek,iommu.yaml
15
16  MediaTek SMI have two generations of HW architecture, here is the list
17  which generation the SoCs use:
18  generation 1: mt2701 and mt7623.
19  generation 2: mt2712, mt6779, mt8167, mt8173, mt8183 and mt8192.
20
21  There's slight differences between the two SMI, for generation 2, the
22  register which control the iommu port is at each larb's register base. But
23  for generation 1, the register is at smi ao base(smi always on register
24  base). Besides that, the smi async clock should be prepared and enabled for
25  SMI generation 1 to transform the smi clock into emi clock domain, but that is
26  not needed for SMI generation 2.
27
28properties:
29  compatible:
30    oneOf:
31      - enum:
32          - mediatek,mt2701-smi-common
33          - mediatek,mt2712-smi-common
34          - mediatek,mt6779-smi-common
35          - mediatek,mt8167-smi-common
36          - mediatek,mt8173-smi-common
37          - mediatek,mt8183-smi-common
38          - mediatek,mt8192-smi-common
39
40      - description: for mt7623
41        items:
42          - const: mediatek,mt7623-smi-common
43          - const: mediatek,mt2701-smi-common
44
45  reg:
46    maxItems: 1
47
48  power-domains:
49    maxItems: 1
50
51  clocks:
52    description: |
53      apb and smi are mandatory. the async is only for generation 1 smi HW.
54      gals(global async local sync) also is optional, see below.
55    minItems: 2
56    maxItems: 4
57    items:
58      - description: apb is Advanced Peripheral Bus clock, It's the clock for
59          setting the register.
60      - description: smi is the clock for transfer data and command.
61      - description: async is asynchronous clock, it help transform the smi
62          clock into the emi clock domain.
63      - description: gals0 is the path0 clock of gals.
64      - description: gals1 is the path1 clock of gals.
65
66  clock-names:
67    minItems: 2
68    maxItems: 4
69
70required:
71  - compatible
72  - reg
73  - power-domains
74  - clocks
75  - clock-names
76
77allOf:
78  - if:  # only for gen1 HW
79      properties:
80        compatible:
81          contains:
82            enum:
83              - mediatek,mt2701-smi-common
84    then:
85      properties:
86        clock:
87          items:
88            minItems: 3
89            maxItems: 3
90        clock-names:
91          items:
92            - const: apb
93            - const: smi
94            - const: async
95
96  - if:  # for gen2 HW that have gals
97      properties:
98        compatible:
99          enum:
100            - mediatek,mt6779-smi-common
101            - mediatek,mt8183-smi-common
102            - mediatek,mt8192-smi-common
103
104    then:
105      properties:
106        clock:
107          items:
108            minItems: 4
109            maxItems: 4
110        clock-names:
111          items:
112            - const: apb
113            - const: smi
114            - const: gals0
115            - const: gals1
116
117    else:  # for gen2 HW that don't have gals
118      properties:
119        clock:
120          items:
121            minItems: 2
122            maxItems: 2
123        clock-names:
124          items:
125            - const: apb
126            - const: smi
127
128additionalProperties: false
129
130examples:
131  - |+
132    #include <dt-bindings/clock/mt8173-clk.h>
133    #include <dt-bindings/power/mt8173-power.h>
134
135    smi_common: smi@14022000 {
136            compatible = "mediatek,mt8173-smi-common";
137            reg = <0x14022000 0x1000>;
138            power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
139            clocks = <&mmsys CLK_MM_SMI_COMMON>,
140                     <&mmsys CLK_MM_SMI_COMMON>;
141            clock-names = "apb", "smi";
142    };
143