1Freescale Multi Mode DDR controller (MMDC) 2 3Required properties : 4- compatible : should be one of following: 5 for i.MX6Q/i.MX6DL: 6 - "fsl,imx6q-mmdc"; 7 for i.MX6QP: 8 - "fsl,imx6qp-mmdc", "fsl,imx6q-mmdc"; 9 for i.MX6SL: 10 - "fsl,imx6sl-mmdc", "fsl,imx6q-mmdc"; 11 for i.MX6SLL: 12 - "fsl,imx6sll-mmdc", "fsl,imx6q-mmdc"; 13 for i.MX6SX: 14 - "fsl,imx6sx-mmdc", "fsl,imx6q-mmdc"; 15 for i.MX6UL/i.MX6ULL/i.MX6ULZ: 16 - "fsl,imx6ul-mmdc", "fsl,imx6q-mmdc"; 17 for i.MX7ULP: 18 - "fsl,imx7ulp-mmdc", "fsl,imx6q-mmdc"; 19- reg : address and size of MMDC DDR controller registers 20 21Optional properties : 22- clocks : the clock provided by the SoC to access the MMDC registers 23 24Example : 25 mmdc0: memory-controller@21b0000 { /* MMDC0 */ 26 compatible = "fsl,imx6q-mmdc"; 27 reg = <0x021b0000 0x4000>; 28 clocks = <&clks IMX6QDL_CLK_MMDC_P0_IPG>; 29 }; 30 31 mmdc1: memory-controller@21b4000 { /* MMDC1 */ 32 compatible = "fsl,imx6q-mmdc"; 33 reg = <0x021b4000 0x4000>; 34 status = "disabled"; 35 }; 36