1* Exynos5422 frequency and voltage scaling for Dynamic Memory Controller device 2 3The Samsung Exynos5422 SoC has DMC (Dynamic Memory Controller) to which the DRAM 4memory chips are connected. The driver is to monitor the controller in runtime 5and switch frequency and voltage. To monitor the usage of the controller in 6runtime, the driver uses the PPMU (Platform Performance Monitoring Unit), which 7is able to measure the current load of the memory. 8When 'userspace' governor is used for the driver, an application is able to 9switch the DMC and memory frequency. 10 11Required properties for DMC device for Exynos5422: 12- compatible: Should be "samsung,exynos5422-dmc". 13- clocks : list of clock specifiers, must contain an entry for each 14 required entry in clock-names for CLK_FOUT_SPLL, CLK_MOUT_SCLK_SPLL, 15 CLK_FF_DOUT_SPLL2, CLK_FOUT_BPLL, CLK_MOUT_BPLL, CLK_SCLK_BPLL, 16 CLK_MOUT_MX_MSPLL_CCORE, CLK_MOUT_MX_MSPLL_CCORE_PHY, CLK_MOUT_MCLK_CDREX, 17- clock-names : should include "fout_spll", "mout_sclk_spll", "ff_dout_spll2", 18 "fout_bpll", "mout_bpll", "sclk_bpll", "mout_mx_mspll_ccore", 19 "mout_mclk_cdrex" entries 20- devfreq-events : phandles for PPMU devices connected to this DMC. 21- vdd-supply : phandle for voltage regulator which is connected. 22- reg : registers of two CDREX controllers. 23- operating-points-v2 : phandle for OPPs described in v2 definition. 24- device-handle : phandle of the connected DRAM memory device. For more 25 information please refer to documentation file: 26 Documentation/devicetree/bindings/ddr/lpddr3.txt 27- devfreq-events : phandles of the PPMU events used by the controller. 28- samsung,syscon-clk : phandle of the clock register set used by the controller, 29 these registers are used for enabling a 'pause' feature and are not 30 exposed by clock framework but they must be used in a safe way. 31 The register offsets are in the driver code and specyfic for this SoC 32 type. 33 34Optional properties for DMC device for Exynos5422: 35- interrupt-parent : The parent interrupt controller. 36- interrupts : Contains the IRQ line numbers for the DMC internal performance 37 event counters in DREX0 and DREX1 channels. Align with specification of the 38 interrupt line(s) in the interrupt-parent controller. 39- interrupt-names : IRQ names "drex_0" and "drex_1", the order should be the 40 same as in the 'interrupts' list above. 41 42Example: 43 44 ppmu_dmc0_0: ppmu@10d00000 { 45 compatible = "samsung,exynos-ppmu"; 46 reg = <0x10d00000 0x2000>; 47 clocks = <&clock CLK_PCLK_PPMU_DREX0_0>; 48 clock-names = "ppmu"; 49 events { 50 ppmu_event_dmc0_0: ppmu-event3-dmc0_0 { 51 event-name = "ppmu-event3-dmc0_0"; 52 }; 53 }; 54 }; 55 56 dmc: memory-controller@10c20000 { 57 compatible = "samsung,exynos5422-dmc"; 58 reg = <0x10c20000 0x10000>, <0x10c30000 0x10000>; 59 clocks = <&clock CLK_FOUT_SPLL>, 60 <&clock CLK_MOUT_SCLK_SPLL>, 61 <&clock CLK_FF_DOUT_SPLL2>, 62 <&clock CLK_FOUT_BPLL>, 63 <&clock CLK_MOUT_BPLL>, 64 <&clock CLK_SCLK_BPLL>, 65 <&clock CLK_MOUT_MX_MSPLL_CCORE>, 66 <&clock CLK_MOUT_MCLK_CDREX>; 67 clock-names = "fout_spll", 68 "mout_sclk_spll", 69 "ff_dout_spll2", 70 "fout_bpll", 71 "mout_bpll", 72 "sclk_bpll", 73 "mout_mx_mspll_ccore", 74 "mout_mclk_cdrex"; 75 operating-points-v2 = <&dmc_opp_table>; 76 devfreq-events = <&ppmu_event3_dmc0_0>, <&ppmu_event3_dmc0_1>, 77 <&ppmu_event3_dmc1_0>, <&ppmu_event3_dmc1_1>; 78 device-handle = <&samsung_K3QF2F20DB>; 79 vdd-supply = <&buck1_reg>; 80 samsung,syscon-clk = <&clock>; 81 interrupt-parent = <&combiner>; 82 interrupts = <16 0>, <16 1>; 83 interrupt-names = "drex_0", "drex_1"; 84 }; 85