1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/memory-controllers/ddr/jedec,lpddr2.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: LPDDR2 SDRAM compliant to JEDEC JESD209-2 8 9maintainers: 10 - Krzysztof Kozlowski <krzk@kernel.org> 11 12properties: 13 compatible: 14 oneOf: 15 - items: 16 - enum: 17 - elpida,ECB240ABACN 18 - elpida,B8132B2PB-6D-F 19 - enum: 20 - jedec,lpddr2-s4 21 - items: 22 - enum: 23 - jedec,lpddr2-s2 24 - items: 25 - enum: 26 - jedec,lpddr2-nvm 27 28 revision-id1: 29 $ref: /schemas/types.yaml#/definitions/uint32 30 maximum: 255 31 description: | 32 Revision 1 value of SDRAM chip. Obtained from device datasheet. 33 Property is deprecated, use revision-id instead. 34 deprecated: true 35 36 revision-id2: 37 $ref: /schemas/types.yaml#/definitions/uint32 38 maximum: 255 39 description: | 40 Revision 2 value of SDRAM chip. Obtained from device datasheet. 41 Property is deprecated, use revision-id instead. 42 deprecated: true 43 44 revision-id: 45 $ref: /schemas/types.yaml#/definitions/uint32-array 46 description: | 47 Revision IDs read from Mode Register 6 and 7. One byte per uint32 cell (i.e. <MR6 MR7>). 48 minItems: 2 49 maxItems: 2 50 items: 51 minimum: 0 52 maximum: 255 53 54 density: 55 $ref: /schemas/types.yaml#/definitions/uint32 56 description: | 57 Density in megabits of SDRAM chip. Obtained from device datasheet. 58 enum: 59 - 64 60 - 128 61 - 256 62 - 512 63 - 1024 64 - 2048 65 - 4096 66 - 8192 67 - 16384 68 - 32768 69 70 io-width: 71 $ref: /schemas/types.yaml#/definitions/uint32 72 description: | 73 IO bus width in bits of SDRAM chip. Obtained from device datasheet. 74 enum: 75 - 32 76 - 16 77 - 8 78 79 tRRD-min-tck: 80 $ref: /schemas/types.yaml#/definitions/uint32 81 maximum: 16 82 description: | 83 Active bank a to active bank b in terms of number of clock cycles. 84 Obtained from device datasheet. 85 86 tWTR-min-tck: 87 $ref: /schemas/types.yaml#/definitions/uint32 88 maximum: 16 89 description: | 90 Internal WRITE-to-READ command delay in terms of number of clock cycles. 91 Obtained from device datasheet. 92 93 tXP-min-tck: 94 $ref: /schemas/types.yaml#/definitions/uint32 95 maximum: 16 96 description: | 97 Exit power-down to next valid command delay in terms of number of clock 98 cycles. Obtained from device datasheet. 99 100 tRTP-min-tck: 101 $ref: /schemas/types.yaml#/definitions/uint32 102 maximum: 16 103 description: | 104 Internal READ to PRECHARGE command delay in terms of number of clock 105 cycles. Obtained from device datasheet. 106 107 tCKE-min-tck: 108 $ref: /schemas/types.yaml#/definitions/uint32 109 maximum: 16 110 description: | 111 CKE minimum pulse width (HIGH and LOW pulse width) in terms of number 112 of clock cycles. Obtained from device datasheet. 113 114 tRPab-min-tck: 115 $ref: /schemas/types.yaml#/definitions/uint32 116 maximum: 16 117 description: | 118 Row precharge time (all banks) in terms of number of clock cycles. 119 Obtained from device datasheet. 120 121 tRCD-min-tck: 122 $ref: /schemas/types.yaml#/definitions/uint32 123 maximum: 16 124 description: | 125 RAS-to-CAS delay in terms of number of clock cycles. Obtained from 126 device datasheet. 127 128 tWR-min-tck: 129 $ref: /schemas/types.yaml#/definitions/uint32 130 maximum: 16 131 description: | 132 WRITE recovery time in terms of number of clock cycles. Obtained from 133 device datasheet. 134 135 tRASmin-min-tck: 136 $ref: /schemas/types.yaml#/definitions/uint32 137 maximum: 16 138 description: | 139 Row active time in terms of number of clock cycles. Obtained from device 140 datasheet. 141 142 tCKESR-min-tck: 143 $ref: /schemas/types.yaml#/definitions/uint32 144 maximum: 16 145 description: | 146 CKE minimum pulse width during SELF REFRESH (low pulse width during 147 SELF REFRESH) in terms of number of clock cycles. Obtained from device 148 datasheet. 149 150 tFAW-min-tck: 151 $ref: /schemas/types.yaml#/definitions/uint32 152 maximum: 16 153 description: | 154 Four-bank activate window in terms of number of clock cycles. Obtained 155 from device datasheet. 156 157patternProperties: 158 "^lpddr2-timings": 159 $ref: jedec,lpddr2-timings.yaml 160 description: | 161 The lpddr2 node may have one or more child nodes of type "lpddr2-timings". 162 "lpddr2-timings" provides AC timing parameters of the device for 163 a given speed-bin. The user may provide the timings for as many 164 speed-bins as is required. 165 166required: 167 - compatible 168 - density 169 - io-width 170 171additionalProperties: false 172 173examples: 174 - | 175 elpida_ECB240ABACN: lpddr2 { 176 compatible = "elpida,ECB240ABACN", "jedec,lpddr2-s4"; 177 density = <2048>; 178 io-width = <32>; 179 revision-id = <1 0>; 180 181 tRPab-min-tck = <3>; 182 tRCD-min-tck = <3>; 183 tWR-min-tck = <3>; 184 tRASmin-min-tck = <3>; 185 tRRD-min-tck = <2>; 186 tWTR-min-tck = <2>; 187 tXP-min-tck = <2>; 188 tRTP-min-tck = <2>; 189 tCKE-min-tck = <3>; 190 tCKESR-min-tck = <3>; 191 tFAW-min-tck = <8>; 192 193 timings_elpida_ECB240ABACN_400mhz: lpddr2-timings0 { 194 compatible = "jedec,lpddr2-timings"; 195 min-freq = <10000000>; 196 max-freq = <400000000>; 197 tRPab = <21000>; 198 tRCD = <18000>; 199 tWR = <15000>; 200 tRAS-min = <42000>; 201 tRRD = <10000>; 202 tWTR = <7500>; 203 tXP = <7500>; 204 tRTP = <7500>; 205 tCKESR = <15000>; 206 tDQSCK-max = <5500>; 207 tFAW = <50000>; 208 tZQCS = <90000>; 209 tZQCL = <360000>; 210 tZQinit = <1000000>; 211 tRAS-max-ns = <70000>; 212 }; 213 214 timings_elpida_ECB240ABACN_200mhz: lpddr2-timings1 { 215 compatible = "jedec,lpddr2-timings"; 216 min-freq = <10000000>; 217 max-freq = <200000000>; 218 tRPab = <21000>; 219 tRCD = <18000>; 220 tWR = <15000>; 221 tRAS-min = <42000>; 222 tRRD = <10000>; 223 tWTR = <10000>; 224 tXP = <7500>; 225 tRTP = <7500>; 226 tCKESR = <15000>; 227 tDQSCK-max = <5500>; 228 tFAW = <50000>; 229 tZQCS = <90000>; 230 tZQCL = <360000>; 231 tZQinit = <1000000>; 232 tRAS-max-ns = <70000>; 233 }; 234 }; 235