xref: /freebsd/sys/contrib/device-tree/Bindings/memory-controllers/brcm,brcmstb-memc-ddr.yaml (revision 833e5d42ab135b0238e61c5b3c19b8619677cbfa)

# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/memory-controllers/brcm,brcmstb-memc-ddr.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Memory controller (MEMC) for Broadcom STB

maintainers:
  - Florian Fainelli <f.fainelli@gmail.com>

properties:
  compatible:
    oneOf:
      - description: Revision > 2.1 controllers
        items:
          - enum:
              - brcm,brcmstb-memc-ddr-rev-b.2.2
              - brcm,brcmstb-memc-ddr-rev-b.2.3
              - brcm,brcmstb-memc-ddr-rev-b.2.5
              - brcm,brcmstb-memc-ddr-rev-b.2.6
              - brcm,brcmstb-memc-ddr-rev-b.2.7
              - brcm,brcmstb-memc-ddr-rev-b.2.8
              - brcm,brcmstb-memc-ddr-rev-b.3.0
              - brcm,brcmstb-memc-ddr-rev-b.3.1
              - brcm,brcmstb-memc-ddr-rev-c.1.0
              - brcm,brcmstb-memc-ddr-rev-c.1.1
              - brcm,brcmstb-memc-ddr-rev-c.1.2
              - brcm,brcmstb-memc-ddr-rev-c.1.3
              - brcm,brcmstb-memc-ddr-rev-c.1.4
          - const: brcm,brcmstb-memc-ddr-rev-b.2.1
          - const: brcm,brcmstb-memc-ddr
      - description: Revision 2.1 controllers
        items:
          - const: brcm,brcmstb-memc-ddr-rev-b.2.1
          - const: brcm,brcmstb-memc-ddr
      - description: Revision 2.0 controllers
        items:
          - const: brcm,brcmstb-memc-ddr-rev-b.2.0
          - const: brcm,brcmstb-memc-ddr
      - description: Revision 1.x controllers
        items:
          - const: brcm,brcmstb-memc-ddr-rev-b.1.x
          - const: brcm,brcmstb-memc-ddr

  reg:
    maxItems: 1

  clock-frequency:
    description: DDR PHY frequency in Hz

required:
  - compatible
  - reg

additionalProperties: false

examples:
  - |
    memory-controller@9902000 {
        compatible = "brcm,brcmstb-memc-ddr-rev-c.1.1",
                     "brcm,brcmstb-memc-ddr-rev-b.2.1",
                     "brcm,brcmstb-memc-ddr";
        reg = <0x9902000 0x600>;
        clock-frequency = <2133000000>;
    };