1Binding for Qualcomm Atheros AR7xxx/AR9xxx DDR controller 2 3The DDR controller of the AR7xxx and AR9xxx families provides an interface 4to flush the FIFO between various devices and the DDR. This is mainly used 5by the IRQ controller to flush the FIFO before running the interrupt handler 6of such devices. 7 8Required properties: 9 10- compatible: has to be "qca,<soc-type>-ddr-controller", 11 "qca,[ar7100|ar7240]-ddr-controller" as fallback. 12 On SoC with PCI support "qca,ar7100-ddr-controller" should be used as 13 fallback, otherwise "qca,ar7240-ddr-controller" should be used. 14- reg: Base address and size of the controller's memory area 15- #qca,ddr-wb-channel-cells: Specifies the number of cells needed to encode 16 the write buffer channel index, should be 1. 17 18Example: 19 20 ddr_ctrl: memory-controller@18000000 { 21 compatible = "qca,ar9132-ddr-controller", 22 "qca,ar7240-ddr-controller"; 23 reg = <0x18000000 0x100>; 24 25 #qca,ddr-wb-channel-cells = <1>; 26 }; 27 28 ... 29 30 interrupt-controller { 31 ... 32 qca,ddr-wb-channel-interrupts = <2>, <3>, <4>, <5>; 33 qca,ddr-wb-channels = <&ddr_ctrl 3>, <&ddr_ctrl 2>, 34 <&ddr_ctrl 0>, <&ddr_ctrl 1>; 35 }; 36