1DT bindings for Xilinx video IP cores 2------------------------------------- 3 4Xilinx video IP cores process video streams by acting as video sinks and/or 5sources. They are connected by links through their input and output ports, 6creating a video pipeline. 7 8Each video IP core is represented by an AMBA bus child node in the device 9tree using bindings documented in this directory. Connections between the IP 10cores are represented as defined in ../video-interfaces.txt. 11 12The whole pipeline is represented by an AMBA bus child node in the device 13tree using bindings documented in ./xlnx,video.txt. 14 15Common properties 16----------------- 17 18The following properties are common to all Xilinx video IP cores. 19 20- xlnx,video-format: This property represents a video format transmitted on an 21 AXI bus between video IP cores, using its VF code as defined in "AXI4-Stream 22 Video IP and System Design Guide" [UG934]. How the format relates to the IP 23 core is described in the IP core bindings documentation. 24 25- xlnx,video-width: This property qualifies the video format with the sample 26 width expressed as a number of bits per pixel component. All components must 27 use the same width. 28 29- xlnx,cfa-pattern: When the video format is set to Mono/Sensor, this property 30 describes the sensor's color filter array pattern. Supported values are 31 "bggr", "gbrg", "grbg", "rggb" and "mono". If not specified, the pattern 32 defaults to "mono". 33 34 35[UG934] https://www.xilinx.com/support/documentation/ip_documentation/axi_videoip/v1_0/ug934_axi_videoIP.pdf 36