xref: /freebsd/sys/contrib/device-tree/Bindings/media/rockchip-vpu.yaml (revision b197d4b893974c9eb4d7b38704c6d5c486235d6f) 
1# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
2
3%YAML 1.2
4---
5$id: "http://devicetree.org/schemas/media/rockchip-vpu.yaml#"
6$schema: "http://devicetree.org/meta-schemas/core.yaml#"
7
8title: Hantro G1 VPU codecs implemented on Rockchip SoCs
9
10maintainers:
11  - Ezequiel Garcia <ezequiel@collabora.com>
12
13description:
14  Hantro G1 video encode and decode accelerators present on Rockchip SoCs.
15
16properties:
17  compatible:
18    oneOf:
19      - enum:
20          - rockchip,rk3036-vpu
21          - rockchip,rk3066-vpu
22          - rockchip,rk3288-vpu
23          - rockchip,rk3328-vpu
24          - rockchip,rk3399-vpu
25          - rockchip,px30-vpu
26      - items:
27          - const: rockchip,rk3188-vpu
28          - const: rockchip,rk3066-vpu
29      - items:
30          - const: rockchip,rk3228-vpu
31          - const: rockchip,rk3399-vpu
32
33  reg:
34    maxItems: 1
35
36  interrupts:
37    minItems: 1
38    maxItems: 2
39
40  interrupt-names:
41    oneOf:
42      - const: vdpu
43      - items:
44          - const: vepu
45          - const: vdpu
46
47  clocks:
48    oneOf:
49      - maxItems: 2
50      - maxItems: 4
51
52  clock-names:
53    oneOf:
54      - items:
55          - const: aclk
56          - const: hclk
57      - items:
58          - const: aclk_vdpu
59          - const: hclk_vdpu
60          - const: aclk_vepu
61          - const: hclk_vepu
62
63  power-domains:
64    maxItems: 1
65
66  iommus:
67    maxItems: 1
68
69required:
70  - compatible
71  - reg
72  - interrupts
73  - interrupt-names
74  - clocks
75  - clock-names
76
77additionalProperties: false
78
79examples:
80  - |
81        #include <dt-bindings/clock/rk3288-cru.h>
82        #include <dt-bindings/interrupt-controller/arm-gic.h>
83        #include <dt-bindings/power/rk3288-power.h>
84
85        vpu: video-codec@ff9a0000 {
86                compatible = "rockchip,rk3288-vpu";
87                reg = <0xff9a0000 0x800>;
88                interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
89                             <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
90                interrupt-names = "vepu", "vdpu";
91                clocks = <&cru ACLK_VCODEC>, <&cru HCLK_VCODEC>;
92                clock-names = "aclk", "hclk";
93                power-domains = <&power RK3288_PD_VIDEO>;
94                iommus = <&vpu_mmu>;
95        };
96