xref: /freebsd/sys/contrib/device-tree/Bindings/media/rockchip-isp1.yaml (revision 6580f5c38dd5b01aeeaed16b370f1a12423437f0) 
1# SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/media/rockchip-isp1.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Rockchip SoC Image Signal Processing unit v1
8
9maintainers:
10  - Helen Koike <helen.koike@collabora.com>
11
12description: |
13  Rockchip ISP1 is the Camera interface for the Rockchip series of SoCs
14  which contains image processing, scaling, and compression functions.
15
16properties:
17  compatible:
18    enum:
19      - rockchip,px30-cif-isp
20      - rockchip,rk3399-cif-isp
21
22  reg:
23    maxItems: 1
24
25  interrupts:
26    minItems: 1
27    maxItems: 3
28
29  interrupt-names:
30    items:
31      - const: isp
32      - const: mi
33      - const: mipi
34
35  clocks:
36    minItems: 3
37    items:
38      # isp0 and isp1
39      - description: ISP clock
40      - description: ISP AXI clock
41      - description: ISP AHB clock
42      # only for isp1
43      - description: ISP Pixel clock
44
45  clock-names:
46    minItems: 3
47    items:
48      # isp0 and isp1
49      - const: isp
50      - const: aclk
51      - const: hclk
52      # only for isp1
53      - const: pclk
54
55  iommus:
56    maxItems: 1
57
58  phys:
59    maxItems: 1
60    description: phandle for the PHY port
61
62  phy-names:
63    const: dphy
64
65  power-domains:
66    maxItems: 1
67
68  ports:
69    $ref: /schemas/graph.yaml#/properties/ports
70
71    properties:
72      port@0:
73        $ref: /schemas/graph.yaml#/$defs/port-base
74        unevaluatedProperties: false
75        description: connection point for sensors at MIPI-DPHY RX0
76
77        properties:
78          endpoint:
79            $ref: video-interfaces.yaml#
80            unevaluatedProperties: false
81
82            properties:
83              data-lanes:
84                minItems: 1
85                maxItems: 4
86
87      port@1:
88        $ref: /schemas/graph.yaml#/$defs/port-base
89        unevaluatedProperties: false
90        description: connection point for input on the parallel interface
91
92        properties:
93          endpoint:
94            $ref: video-interfaces.yaml#
95            unevaluatedProperties: false
96
97            properties:
98              bus-type:
99                enum: [5, 6]
100
101            required:
102              - bus-type
103
104    anyOf:
105      - required:
106          - port@0
107      - required:
108          - port@1
109
110required:
111  - compatible
112  - reg
113  - interrupts
114  - clocks
115  - clock-names
116  - iommus
117  - phys
118  - phy-names
119  - power-domains
120  - ports
121
122allOf:
123  - if:
124      properties:
125        compatible:
126          contains:
127            const: rockchip,rk3399-cif-isp
128    then:
129      properties:
130        clocks:
131          minItems: 3
132          maxItems: 4
133        clock-names:
134          minItems: 3
135          maxItems: 4
136
137  - if:
138      properties:
139        compatible:
140          contains:
141            const: rockchip,px30-cif-isp
142    then:
143      required:
144        - interrupt-names
145
146additionalProperties: false
147
148examples:
149  - |
150
151    #include <dt-bindings/clock/rk3399-cru.h>
152    #include <dt-bindings/interrupt-controller/arm-gic.h>
153    #include <dt-bindings/power/rk3399-power.h>
154
155    parent0: parent {
156        #address-cells = <2>;
157        #size-cells = <2>;
158
159        isp0: isp0@ff910000 {
160            compatible = "rockchip,rk3399-cif-isp";
161            reg = <0x0 0xff910000 0x0 0x4000>;
162            interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH 0>;
163            clocks = <&cru SCLK_ISP0>,
164                     <&cru ACLK_ISP0_WRAPPER>,
165                     <&cru HCLK_ISP0_WRAPPER>;
166            clock-names = "isp", "aclk", "hclk";
167            iommus = <&isp0_mmu>;
168            phys = <&dphy>;
169            phy-names = "dphy";
170            power-domains = <&power RK3399_PD_ISP0>;
171
172            ports {
173                #address-cells = <1>;
174                #size-cells = <0>;
175
176                port@0 {
177                    reg = <0>;
178                    #address-cells = <1>;
179                    #size-cells = <0>;
180
181                    mipi_in_wcam: endpoint@0 {
182                        reg = <0>;
183                        remote-endpoint = <&wcam_out>;
184                        data-lanes = <1 2>;
185                    };
186
187                    mipi_in_ucam: endpoint@1 {
188                        reg = <1>;
189                        remote-endpoint = <&ucam_out>;
190                        data-lanes = <1>;
191                    };
192                };
193            };
194        };
195
196        i2c7: i2c {
197            #address-cells = <1>;
198            #size-cells = <0>;
199
200            wcam: camera@36 {
201                compatible = "ovti,ov5695";
202                reg = <0x36>;
203                clocks = <&cru SCLK_TESTCLKOUT1>;
204
205                port {
206                    wcam_out: endpoint {
207                        remote-endpoint = <&mipi_in_wcam>;
208                        data-lanes = <1 2>;
209                    };
210                };
211            };
212
213            ucam: camera@3c {
214                compatible = "ovti,ov2685";
215                reg = <0x3c>;
216
217                clocks = <&cru SCLK_TESTCLKOUT1>;
218                clock-names = "xvclk";
219
220                avdd-supply = <&pp2800_cam>;
221                dovdd-supply = <&pp1800>;
222                dvdd-supply = <&pp1800>;
223
224                port {
225                    ucam_out: endpoint {
226                        remote-endpoint = <&mipi_in_ucam>;
227                        data-lanes = <1>;
228                    };
229                };
230            };
231        };
232    };
233
234  - |
235
236    #include <dt-bindings/interrupt-controller/arm-gic.h>
237    #include <dt-bindings/power/px30-power.h>
238
239    parent1: parent {
240        #address-cells = <2>;
241        #size-cells = <2>;
242
243        isp: isp@ff4a0000 {
244            compatible = "rockchip,px30-cif-isp";
245            reg = <0x0 0xff4a0000 0x0 0x8000>;
246            interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
247                         <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,
248                         <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
249            interrupt-names = "isp", "mi", "mipi";
250            clocks = <&cru SCLK_ISP0>,
251                     <&cru ACLK_ISP0_WRAPPER>,
252                     <&cru HCLK_ISP0_WRAPPER>,
253                     <&cru PCLK_ISP1_WRAPPER>;
254            clock-names = "isp", "aclk", "hclk", "pclk";
255            iommus = <&isp_mmu>;
256            phys = <&csi_dphy>;
257            phy-names = "dphy";
258            power-domains = <&power PX30_PD_VI>;
259
260            ports {
261                #address-cells = <1>;
262                #size-cells = <0>;
263
264                port@0 {
265                    reg = <0>;
266                    #address-cells = <1>;
267                    #size-cells = <0>;
268
269                    mipi_in_ucam1: endpoint@0 {
270                        reg = <0>;
271                        remote-endpoint = <&ucam1_out>;
272                        data-lanes = <1 2>;
273                    };
274                };
275            };
276        };
277
278        i2c2: i2c {
279            #address-cells = <1>;
280            #size-cells = <0>;
281
282            ov5695: camera@36 {
283                compatible = "ovti,ov5647";
284                reg = <0x36>;
285                clocks = <&cru SCLK_CIF_OUT>;
286
287                port {
288                    ucam1_out: endpoint {
289                        remote-endpoint = <&mipi_in_ucam1>;
290                        data-lanes = <1 2>;
291                    };
292                };
293            };
294        };
295    };
296