1# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/media/renesas,vsp1.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: Renesas VSP Video Processing Engine 8 9maintainers: 10 - Laurent Pinchart <laurent.pinchart@ideasonboard.com> 11 12description: 13 The VSP is a video processing engine that supports up-/down-scaling, alpha 14 blending, color space conversion and various other image processing features. 15 It can be found in the Renesas R-Car Gen2, R-Car Gen3, RZ/G1, and RZ/G2 SoCs. 16 17properties: 18 compatible: 19 oneOf: 20 - enum: 21 - renesas,r9a07g044-vsp2 # RZ/G2L 22 - renesas,vsp1 # R-Car Gen2 and RZ/G1 23 - renesas,vsp2 # R-Car Gen3 and RZ/G2 24 - items: 25 - enum: 26 - renesas,r9a07g043u-vsp2 # RZ/G2UL 27 - renesas,r9a07g054-vsp2 # RZ/V2L 28 - renesas,r9a09g056-vsp2 # RZ/V2N 29 - renesas,r9a09g057-vsp2 # RZ/V2H(P) 30 - const: renesas,r9a07g044-vsp2 # RZ/G2L fallback 31 32 reg: 33 maxItems: 1 34 35 interrupts: 36 maxItems: 1 37 38 clocks: 39 minItems: 1 40 items: 41 - description: Main clock 42 - description: Register access clock 43 - description: Video clock 44 45 clock-names: 46 items: 47 - const: aclk 48 - const: pclk 49 - const: vclk 50 51 power-domains: 52 maxItems: 1 53 54 resets: 55 maxItems: 1 56 57 renesas,fcp: 58 $ref: /schemas/types.yaml#/definitions/phandle 59 description: 60 A phandle referencing the FCP that handles memory accesses for the VSP. 61 62required: 63 - compatible 64 - reg 65 - interrupts 66 - clocks 67 - power-domains 68 - resets 69 70additionalProperties: false 71 72allOf: 73 - if: 74 properties: 75 compatible: 76 contains: 77 const: renesas,vsp1 78 then: 79 properties: 80 renesas,fcp: false 81 else: 82 required: 83 - renesas,fcp 84 85 - if: 86 properties: 87 compatible: 88 contains: 89 const: renesas,r9a07g044-vsp2 90 then: 91 properties: 92 clocks: 93 minItems: 3 94 required: 95 - clock-names 96 else: 97 properties: 98 clocks: 99 maxItems: 1 100 clock-names: false 101 102examples: 103 # R8A7790 (R-Car H2) VSP1-S 104 - | 105 #include <dt-bindings/clock/renesas-cpg-mssr.h> 106 #include <dt-bindings/interrupt-controller/arm-gic.h> 107 #include <dt-bindings/power/r8a7790-sysc.h> 108 109 vsp@fe928000 { 110 compatible = "renesas,vsp1"; 111 reg = <0xfe928000 0x8000>; 112 interrupts = <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>; 113 clocks = <&cpg CPG_MOD 131>; 114 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; 115 resets = <&cpg 131>; 116 }; 117 118 # R8A77951 (R-Car H3) VSP2-BC 119 - | 120 #include <dt-bindings/clock/renesas-cpg-mssr.h> 121 #include <dt-bindings/interrupt-controller/arm-gic.h> 122 #include <dt-bindings/power/r8a7795-sysc.h> 123 124 vsp@fe920000 { 125 compatible = "renesas,vsp2"; 126 reg = <0xfe920000 0x8000>; 127 interrupts = <GIC_SPI 465 IRQ_TYPE_LEVEL_HIGH>; 128 clocks = <&cpg CPG_MOD 624>; 129 power-domains = <&sysc R8A7795_PD_A3VP>; 130 resets = <&cpg 624>; 131 132 renesas,fcp = <&fcpvb1>; 133 }; 134... 135