1Renesas R-Car Fine Display Processor (FDP1) 2------------------------------------------- 3 4The FDP1 is a de-interlacing module which converts interlaced video to 5progressive video. It is capable of performing pixel format conversion between 6YCbCr/YUV formats and RGB formats. Only YCbCr/YUV formats are supported as 7an input to the module. 8 9Required properties: 10 11 - compatible: must be "renesas,fdp1" 12 - reg: the register base and size for the device registers 13 - interrupts : interrupt specifier for the FDP1 instance 14 - clocks: reference to the functional clock 15 16Optional properties: 17 18 - power-domains: reference to the power domain that the FDP1 belongs to, if 19 any. 20 - renesas,fcp: a phandle referencing the FCP that handles memory accesses 21 for the FDP1. Not needed on Gen2, mandatory on Gen3. 22 23Please refer to the binding documentation for the clock and/or power domain 24providers for more details. 25 26 27Device node example 28------------------- 29 30 fdp1@fe940000 { 31 compatible = "renesas,fdp1"; 32 reg = <0 0xfe940000 0 0x2400>; 33 interrupts = <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>; 34 clocks = <&cpg CPG_MOD 119>; 35 power-domains = <&sysc R8A7795_PD_A3VP>; 36 renesas,fcp = <&fcpf0>; 37 }; 38