1# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/media/renesas,drif.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: Renesas R-Car Gen3 Digital Radio Interface Controller (DRIF) 8 9maintainers: 10 - Ramesh Shanmugasundaram <rashanmu@gmail.com> 11 - Fabrizio Castro <fabrizio.castro.jz@renesas.com> 12 13description: | 14 R-Car Gen3 DRIF is a SPI like receive only slave device. A general 15 representation of DRIF interfacing with a master device is shown below. 16 17 +---------------------+ +---------------------+ 18 | |-----SCK------->|CLK | 19 | Master |-----SS-------->|SYNC DRIFn (slave) | 20 | |-----SD0------->|D0 | 21 | |-----SD1------->|D1 | 22 +---------------------+ +---------------------+ 23 24 As per datasheet, each DRIF channel (drifn) is made up of two internal 25 channels (drifn0 & drifn1). These two internal channels share the common 26 CLK & SYNC. Each internal channel has its own dedicated resources like 27 irq, dma channels, address space & clock. This internal split is not 28 visible to the external master device. 29 30 The device tree model represents each internal channel as a separate node. 31 The internal channels sharing the CLK & SYNC are tied together by their 32 phandles using a property called "renesas,bonding". For the rest of 33 the documentation, unless explicitly stated, the word channel implies an 34 internal channel. 35 36 When both internal channels are enabled they need to be managed together 37 as one (i.e.) they cannot operate alone as independent devices. Out of the 38 two, one of them needs to act as a primary device that accepts common 39 properties of both the internal channels. This channel is identified by a 40 property called "renesas,primary-bond". 41 42 To summarize, 43 * When both the internal channels that are bonded together are enabled, 44 the zeroth channel is selected as primary-bond. This channels accepts 45 properties common to all the members of the bond. 46 * When only one of the bonded channels need to be enabled, the property 47 "renesas,bonding" or "renesas,primary-bond" will have no effect. That 48 enabled channel can act alone as any other independent device. 49 50properties: 51 compatible: 52 items: 53 - enum: 54 - renesas,r8a7795-drif # R-Car H3 55 - renesas,r8a7796-drif # R-Car M3-W 56 - renesas,r8a77965-drif # R-Car M3-N 57 - renesas,r8a77990-drif # R-Car E3 58 - const: renesas,rcar-gen3-drif # Generic R-Car Gen3 compatible device 59 60 reg: 61 maxItems: 1 62 63 interrupts: 64 maxItems: 1 65 66 clocks: 67 maxItems: 1 68 69 clock-names: 70 const: fck 71 72 resets: 73 maxItems: 1 74 75 dmas: 76 minItems: 1 77 maxItems: 2 78 79 dma-names: 80 minItems: 1 81 maxItems: 2 82 items: 83 - const: rx 84 - const: rx 85 86 renesas,bonding: 87 $ref: /schemas/types.yaml#/definitions/phandle 88 description: 89 The phandle to the other internal channel of DRIF 90 91 power-domains: 92 maxItems: 1 93 94 renesas,primary-bond: 95 type: boolean 96 description: 97 Indicates that the channel acts as primary among the bonded channels. 98 99 port: 100 $ref: /schemas/graph.yaml#/properties/port 101 unevaluatedProperties: false 102 description: 103 Child port node corresponding to the data input. The port node must 104 contain at least one endpoint. 105 106 properties: 107 endpoint: 108 $ref: /schemas/graph.yaml#/$defs/endpoint-base 109 unevaluatedProperties: false 110 111 properties: 112 sync-active: 113 $ref: /schemas/types.yaml#/definitions/uint32 114 enum: [0, 1] 115 description: 116 Indicates sync signal polarity, 0/1 for low/high respectively. 117 This property maps to SYNCAC bit in the hardware manual. The 118 default is 1 (active high). 119 120required: 121 - compatible 122 - reg 123 - interrupts 124 - clocks 125 - clock-names 126 - resets 127 - dmas 128 - dma-names 129 - renesas,bonding 130 - power-domains 131 132allOf: 133 - if: 134 required: 135 - renesas,primary-bond 136 then: 137 required: 138 - pinctrl-0 139 - pinctrl-names 140 - port 141 142 - if: 143 required: 144 - port 145 then: 146 required: 147 - pinctrl-0 148 - pinctrl-names 149 else: 150 properties: 151 pinctrl-0: false 152 pinctrl-names: false 153 154additionalProperties: false 155 156examples: 157 # Example with both internal channels enabled. 158 # 159 # When interfacing with a third party tuner device with two data pins as shown 160 # below. 161 # 162 # +---------------------+ +---------------------+ 163 # | |-----SCK------->|CLK | 164 # | Master |-----SS-------->|SYNC DRIFn (slave) | 165 # | |-----SD0------->|D0 | 166 # | |-----SD1------->|D1 | 167 # +---------------------+ +---------------------+ 168 - | 169 #include <dt-bindings/clock/r8a7795-cpg-mssr.h> 170 #include <dt-bindings/interrupt-controller/arm-gic.h> 171 #include <dt-bindings/power/r8a7795-sysc.h> 172 173 soc { 174 #address-cells = <2>; 175 #size-cells = <2>; 176 177 drif00: rif@e6f40000 { 178 compatible = "renesas,r8a7795-drif", 179 "renesas,rcar-gen3-drif"; 180 reg = <0 0xe6f40000 0 0x64>; 181 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 182 clocks = <&cpg CPG_MOD 515>; 183 clock-names = "fck"; 184 dmas = <&dmac1 0x20>, <&dmac2 0x20>; 185 dma-names = "rx", "rx"; 186 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 187 renesas,bonding = <&drif01>; 188 resets = <&cpg 515>; 189 renesas,primary-bond; 190 pinctrl-0 = <&drif0_pins>; 191 pinctrl-names = "default"; 192 port { 193 drif0_ep: endpoint { 194 remote-endpoint = <&tuner_ep>; 195 }; 196 }; 197 }; 198 199 drif01: rif@e6f50000 { 200 compatible = "renesas,r8a7795-drif", 201 "renesas,rcar-gen3-drif"; 202 reg = <0 0xe6f50000 0 0x64>; 203 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 204 clocks = <&cpg CPG_MOD 514>; 205 clock-names = "fck"; 206 dmas = <&dmac1 0x22>, <&dmac2 0x22>; 207 dma-names = "rx", "rx"; 208 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 209 renesas,bonding = <&drif00>; 210 resets = <&cpg 514>; 211 }; 212 }; 213 214 # Example with internal channel 1 alone enabled. 215 # 216 # When interfacing with a third party tuner device with one data pin as shown 217 # below. 218 # 219 # +---------------------+ +---------------------+ 220 # | |-----SCK------->|CLK | 221 # | Master |-----SS-------->|SYNC DRIFn (slave) | 222 # | | |D0 (unused) | 223 # | |-----SD-------->|D1 | 224 # +---------------------+ +---------------------+ 225 - | 226 #include <dt-bindings/clock/r8a7795-cpg-mssr.h> 227 #include <dt-bindings/interrupt-controller/arm-gic.h> 228 #include <dt-bindings/power/r8a7795-sysc.h> 229 230 soc { 231 #address-cells = <2>; 232 #size-cells = <2>; 233 234 drif10: rif@e6f60000 { 235 compatible = "renesas,r8a7795-drif", 236 "renesas,rcar-gen3-drif"; 237 reg = <0 0xe6f60000 0 0x64>; 238 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 239 clocks = <&cpg CPG_MOD 513>; 240 clock-names = "fck"; 241 dmas = <&dmac1 0x24>, <&dmac2 0x24>; 242 dma-names = "rx", "rx"; 243 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 244 resets = <&cpg 513>; 245 renesas,bonding = <&drif11>; 246 status = "disabled"; 247 }; 248 249 drif11: rif@e6f70000 { 250 compatible = "renesas,r8a7795-drif", 251 "renesas,rcar-gen3-drif"; 252 reg = <0 0xe6f70000 0 0x64>; 253 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; 254 clocks = <&cpg CPG_MOD 512>; 255 clock-names = "fck"; 256 dmas = <&dmac1 0x26>, <&dmac2 0x26>; 257 dma-names = "rx", "rx"; 258 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 259 resets = <&cpg 512>; 260 renesas,bonding = <&drif10>; 261 pinctrl-0 = <&drif1_pins>; 262 pinctrl-names = "default"; 263 port { 264 drif1_ep: endpoint { 265 remote-endpoint = <&tuner_ep1>; 266 sync-active = <0>; 267 }; 268 }; 269 }; 270 }; 271... 272