xref: /freebsd/sys/contrib/device-tree/Bindings/media/qcom,sm8250-camss.yaml (revision b197d4b893974c9eb4d7b38704c6d5c486235d6f) 
1# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
2
3%YAML 1.2
4---
5$id: "http://devicetree.org/schemas/media/qcom,sm8250-camss.yaml#"
6$schema: "http://devicetree.org/meta-schemas/core.yaml#"
7
8title: Qualcomm CAMSS ISP
9
10maintainers:
11  - Robert Foss <robert.foss@linaro.org>
12
13description: |
14  The CAMSS IP is a CSI decoder and ISP present on Qualcomm platforms.
15
16properties:
17  compatible:
18    const: qcom,sm8250-camss
19
20  clocks:
21    minItems: 37
22    maxItems: 37
23
24  clock-names:
25    items:
26      - const: cam_ahb_clk
27      - const: cam_hf_axi
28      - const: cam_sf_axi
29      - const: camnoc_axi
30      - const: camnoc_axi_src
31      - const: core_ahb
32      - const: cpas_ahb
33      - const: csiphy0
34      - const: csiphy0_timer
35      - const: csiphy1
36      - const: csiphy1_timer
37      - const: csiphy2
38      - const: csiphy2_timer
39      - const: csiphy3
40      - const: csiphy3_timer
41      - const: csiphy4
42      - const: csiphy4_timer
43      - const: csiphy5
44      - const: csiphy5_timer
45      - const: slow_ahb_src
46      - const: vfe0_ahb
47      - const: vfe0_axi
48      - const: vfe0
49      - const: vfe0_cphy_rx
50      - const: vfe0_csid
51      - const: vfe0_areg
52      - const: vfe1_ahb
53      - const: vfe1_axi
54      - const: vfe1
55      - const: vfe1_cphy_rx
56      - const: vfe1_csid
57      - const: vfe1_areg
58      - const: vfe_lite_ahb
59      - const: vfe_lite_axi
60      - const: vfe_lite
61      - const: vfe_lite_cphy_rx
62      - const: vfe_lite_csid
63
64  interrupts:
65    minItems: 14
66    maxItems: 14
67
68  interrupt-names:
69    items:
70      - const: csiphy0
71      - const: csiphy1
72      - const: csiphy2
73      - const: csiphy3
74      - const: csiphy4
75      - const: csiphy5
76      - const: csid0
77      - const: csid1
78      - const: csid2
79      - const: csid3
80      - const: vfe0
81      - const: vfe1
82      - const: vfe_lite0
83      - const: vfe_lite1
84
85  iommus:
86    minItems: 8
87    maxItems: 8
88
89  interconnects:
90    minItems: 4
91    maxItems: 4
92
93  interconnect-names:
94    items:
95      - const: cam_ahb
96      - const: cam_hf_0_mnoc
97      - const: cam_sf_0_mnoc
98      - const: cam_sf_icp_mnoc
99
100  power-domains:
101    items:
102      - description: IFE0 GDSC - Image Front End, Global Distributed Switch Controller.
103      - description: IFE1 GDSC - Image Front End, Global Distributed Switch Controller.
104      - description: Titan GDSC - Titan ISP Block, Global Distributed Switch Controller.
105
106  ports:
107    $ref: /schemas/graph.yaml#/properties/ports
108
109    description:
110      CSI input ports.
111
112    properties:
113      port@0:
114        $ref: /schemas/graph.yaml#/$defs/port-base
115        unevaluatedProperties: false
116        description:
117          Input port for receiving CSI data.
118
119        properties:
120          endpoint:
121            $ref: video-interfaces.yaml#
122            unevaluatedProperties: false
123
124            properties:
125              clock-lanes:
126                maxItems: 1
127
128              data-lanes:
129                minItems: 1
130                maxItems: 4
131
132            required:
133              - clock-lanes
134              - data-lanes
135
136      port@1:
137        $ref: /schemas/graph.yaml#/$defs/port-base
138        unevaluatedProperties: false
139        description:
140          Input port for receiving CSI data.
141
142        properties:
143          endpoint:
144            $ref: video-interfaces.yaml#
145            unevaluatedProperties: false
146
147            properties:
148              clock-lanes:
149                maxItems: 1
150
151              data-lanes:
152                minItems: 1
153                maxItems: 4
154
155            required:
156              - clock-lanes
157              - data-lanes
158
159      port@2:
160        $ref: /schemas/graph.yaml#/$defs/port-base
161        unevaluatedProperties: false
162        description:
163          Input port for receiving CSI data.
164
165        properties:
166          endpoint:
167            $ref: video-interfaces.yaml#
168            unevaluatedProperties: false
169
170            properties:
171              clock-lanes:
172                maxItems: 1
173
174              data-lanes:
175                minItems: 1
176                maxItems: 4
177
178            required:
179              - clock-lanes
180              - data-lanes
181
182      port@3:
183        $ref: /schemas/graph.yaml#/$defs/port-base
184        unevaluatedProperties: false
185        description:
186          Input port for receiving CSI data.
187
188        properties:
189          endpoint:
190            $ref: video-interfaces.yaml#
191            unevaluatedProperties: false
192
193            properties:
194              clock-lanes:
195                maxItems: 1
196
197              data-lanes:
198                minItems: 1
199                maxItems: 4
200
201            required:
202              - clock-lanes
203              - data-lanes
204
205      port@4:
206        $ref: /schemas/graph.yaml#/$defs/port-base
207        unevaluatedProperties: false
208        description:
209          Input port for receiving CSI data.
210
211        properties:
212          endpoint:
213            $ref: video-interfaces.yaml#
214            unevaluatedProperties: false
215
216            properties:
217              clock-lanes:
218                maxItems: 1
219
220              data-lanes:
221                minItems: 1
222                maxItems: 4
223
224            required:
225              - clock-lanes
226              - data-lanes
227
228      port@5:
229        $ref: /schemas/graph.yaml#/$defs/port-base
230        unevaluatedProperties: false
231        description:
232          Input port for receiving CSI data.
233
234        properties:
235          endpoint:
236            $ref: video-interfaces.yaml#
237            unevaluatedProperties: false
238
239            properties:
240              clock-lanes:
241                maxItems: 1
242
243              data-lanes:
244                minItems: 1
245                maxItems: 4
246
247            required:
248              - clock-lanes
249              - data-lanes
250
251  reg:
252    minItems: 10
253    maxItems: 10
254
255  reg-names:
256    items:
257      - const: csiphy0
258      - const: csiphy1
259      - const: csiphy2
260      - const: csiphy3
261      - const: csiphy4
262      - const: csiphy5
263      - const: vfe0
264      - const: vfe1
265      - const: vfe_lite0
266      - const: vfe_lite1
267
268  vdda-phy-supply:
269    description:
270      Phandle to a regulator supply to PHY core block.
271
272  vdda-pll-supply:
273    description:
274      Phandle to 1.8V regulator supply to PHY refclk pll block.
275
276required:
277  - clock-names
278  - clocks
279  - compatible
280  - interconnects
281  - interconnect-names
282  - interrupts
283  - interrupt-names
284  - iommus
285  - power-domains
286  - reg
287  - reg-names
288  - vdda-phy-supply
289  - vdda-pll-supply
290
291additionalProperties: false
292
293examples:
294  - |
295    #include <dt-bindings/interrupt-controller/arm-gic.h>
296    #include <dt-bindings/clock/qcom,camcc-sm8250.h>
297    #include <dt-bindings/interconnect/qcom,sm8250.h>
298    #include <dt-bindings/clock/qcom,gcc-sm8250.h>
299    #include <dt-bindings/power/qcom-rpmpd.h>
300
301    soc {
302        #address-cells = <2>;
303        #size-cells = <2>;
304
305        camss: camss@ac6a000 {
306            compatible = "qcom,sm8250-camss";
307
308            reg = <0 0xac6a000 0 0x2000>,
309                  <0 0xac6c000 0 0x2000>,
310                  <0 0xac6e000 0 0x1000>,
311                  <0 0xac70000 0 0x1000>,
312                  <0 0xac72000 0 0x1000>,
313                  <0 0xac74000 0 0x1000>,
314                  <0 0xacb4000 0 0xd000>,
315                  <0 0xacc3000 0 0xd000>,
316                  <0 0xacd9000 0 0x2200>,
317                  <0 0xacdb200 0 0x2200>;
318            reg-names = "csiphy0",
319                        "csiphy1",
320                        "csiphy2",
321                        "csiphy3",
322                        "csiphy4",
323                        "csiphy5",
324                        "vfe0",
325                        "vfe1",
326                        "vfe_lite0",
327                        "vfe_lite1";
328
329            vdda-phy-supply = <&vreg_l5a_0p88>;
330            vdda-pll-supply = <&vreg_l9a_1p2>;
331
332            interrupts = <GIC_SPI 477 IRQ_TYPE_LEVEL_HIGH>,
333                         <GIC_SPI 478 IRQ_TYPE_LEVEL_HIGH>,
334                         <GIC_SPI 479 IRQ_TYPE_LEVEL_HIGH>,
335                         <GIC_SPI 448 IRQ_TYPE_LEVEL_HIGH>,
336                         <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>,
337                         <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>,
338                         <GIC_SPI 464 IRQ_TYPE_LEVEL_HIGH>,
339                         <GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>,
340                         <GIC_SPI 468 IRQ_TYPE_LEVEL_HIGH>,
341                         <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>,
342                         <GIC_SPI 465 IRQ_TYPE_LEVEL_HIGH>,
343                         <GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH>,
344                         <GIC_SPI 469 IRQ_TYPE_LEVEL_HIGH>,
345                         <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>;
346            interrupt-names = "csiphy0",
347                              "csiphy1",
348                              "csiphy2",
349                              "csiphy3",
350                              "csiphy4",
351                              "csiphy5",
352                              "csid0",
353                              "csid1",
354                              "csid2",
355                              "csid3",
356                              "vfe0",
357                              "vfe1",
358                              "vfe_lite0",
359                              "vfe_lite1";
360
361            power-domains = <&camcc IFE_0_GDSC>,
362                            <&camcc IFE_1_GDSC>,
363                            <&camcc TITAN_TOP_GDSC>;
364
365            clocks = <&gcc GCC_CAMERA_AHB_CLK>,
366                     <&gcc GCC_CAMERA_HF_AXI_CLK>,
367                     <&gcc GCC_CAMERA_SF_AXI_CLK>,
368                     <&camcc CAM_CC_CAMNOC_AXI_CLK>,
369                     <&camcc CAM_CC_CAMNOC_AXI_CLK_SRC>,
370                     <&camcc CAM_CC_CORE_AHB_CLK>,
371                     <&camcc CAM_CC_CPAS_AHB_CLK>,
372                     <&camcc CAM_CC_CSIPHY0_CLK>,
373                     <&camcc CAM_CC_CSI0PHYTIMER_CLK>,
374                     <&camcc CAM_CC_CSIPHY1_CLK>,
375                     <&camcc CAM_CC_CSI1PHYTIMER_CLK>,
376                     <&camcc CAM_CC_CSIPHY2_CLK>,
377                     <&camcc CAM_CC_CSI2PHYTIMER_CLK>,
378                     <&camcc CAM_CC_CSIPHY3_CLK>,
379                     <&camcc CAM_CC_CSI3PHYTIMER_CLK>,
380                     <&camcc CAM_CC_CSIPHY4_CLK>,
381                     <&camcc CAM_CC_CSI4PHYTIMER_CLK>,
382                     <&camcc CAM_CC_CSIPHY5_CLK>,
383                     <&camcc CAM_CC_CSI5PHYTIMER_CLK>,
384                     <&camcc CAM_CC_SLOW_AHB_CLK_SRC>,
385                     <&camcc CAM_CC_IFE_0_AHB_CLK>,
386                     <&camcc CAM_CC_IFE_0_AXI_CLK>,
387                     <&camcc CAM_CC_IFE_0_CLK>,
388                     <&camcc CAM_CC_IFE_0_CPHY_RX_CLK>,
389                     <&camcc CAM_CC_IFE_0_CSID_CLK>,
390                     <&camcc CAM_CC_IFE_0_AREG_CLK>,
391                     <&camcc CAM_CC_IFE_1_AHB_CLK>,
392                     <&camcc CAM_CC_IFE_1_AXI_CLK>,
393                     <&camcc CAM_CC_IFE_1_CLK>,
394                     <&camcc CAM_CC_IFE_1_CPHY_RX_CLK>,
395                     <&camcc CAM_CC_IFE_1_CSID_CLK>,
396                     <&camcc CAM_CC_IFE_1_AREG_CLK>,
397                     <&camcc CAM_CC_IFE_LITE_AHB_CLK>,
398                     <&camcc CAM_CC_IFE_LITE_AXI_CLK>,
399                     <&camcc CAM_CC_IFE_LITE_CLK>,
400                     <&camcc CAM_CC_IFE_LITE_CPHY_RX_CLK>,
401                     <&camcc CAM_CC_IFE_LITE_CSID_CLK>;
402            clock-names = "cam_ahb_clk",
403                          "cam_hf_axi",
404                          "cam_sf_axi",
405                          "camnoc_axi",
406                          "camnoc_axi_src",
407                          "core_ahb",
408                          "cpas_ahb",
409                          "csiphy0",
410                          "csiphy0_timer",
411                          "csiphy1",
412                          "csiphy1_timer",
413                          "csiphy2",
414                          "csiphy2_timer",
415                          "csiphy3",
416                          "csiphy3_timer",
417                          "csiphy4",
418                          "csiphy4_timer",
419                          "csiphy5",
420                          "csiphy5_timer",
421                          "slow_ahb_src",
422                          "vfe0_ahb",
423                          "vfe0_axi",
424                          "vfe0",
425                          "vfe0_cphy_rx",
426                          "vfe0_csid",
427                          "vfe0_areg",
428                          "vfe1_ahb",
429                          "vfe1_axi",
430                          "vfe1",
431                          "vfe1_cphy_rx",
432                          "vfe1_csid",
433                          "vfe1_areg",
434                          "vfe_lite_ahb",
435                          "vfe_lite_axi",
436                          "vfe_lite",
437                          "vfe_lite_cphy_rx",
438                          "vfe_lite_csid";
439
440            iommus = <&apps_smmu 0x800 0x400>,
441                     <&apps_smmu 0x801 0x400>,
442                     <&apps_smmu 0x840 0x400>,
443                     <&apps_smmu 0x841 0x400>,
444                     <&apps_smmu 0xC00 0x400>,
445                     <&apps_smmu 0xC01 0x400>,
446                     <&apps_smmu 0xC40 0x400>,
447                     <&apps_smmu 0xC41 0x400>;
448
449            interconnects = <&gem_noc MASTER_AMPSS_M0 &config_noc SLAVE_CAMERA_CFG>,
450                            <&mmss_noc MASTER_CAMNOC_HF &mc_virt SLAVE_EBI_CH0>,
451                            <&mmss_noc MASTER_CAMNOC_SF &mc_virt SLAVE_EBI_CH0>,
452                            <&mmss_noc MASTER_CAMNOC_ICP &mc_virt SLAVE_EBI_CH0>;
453            interconnect-names = "cam_ahb",
454                                 "cam_hf_0_mnoc",
455                                 "cam_sf_0_mnoc",
456                                 "cam_sf_icp_mnoc";
457
458            ports {
459                #address-cells = <1>;
460                #size-cells = <0>;
461            };
462        };
463    };
464