xref: /freebsd/sys/contrib/device-tree/Bindings/media/qcom,sdm845-camss.yaml (revision 9978553d0199e7ec0bdd1c44fc7f6c7b0c11e43b) 
1# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/media/qcom,sdm845-camss.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Qualcomm CAMSS ISP
8
9maintainers:
10  - Robert Foss <robert.foss@linaro.org>
11
12description: |
13  The CAMSS IP is a CSI decoder and ISP present on Qualcomm platforms
14
15properties:
16  compatible:
17    const: qcom,sdm845-camss
18
19  clocks:
20    minItems: 36
21    maxItems: 36
22
23  clock-names:
24    items:
25      - const: camnoc_axi
26      - const: cpas_ahb
27      - const: cphy_rx_src
28      - const: csi0
29      - const: csi0_src
30      - const: csi1
31      - const: csi1_src
32      - const: csi2
33      - const: csi2_src
34      - const: csiphy0
35      - const: csiphy0_timer
36      - const: csiphy0_timer_src
37      - const: csiphy1
38      - const: csiphy1_timer
39      - const: csiphy1_timer_src
40      - const: csiphy2
41      - const: csiphy2_timer
42      - const: csiphy2_timer_src
43      - const: csiphy3
44      - const: csiphy3_timer
45      - const: csiphy3_timer_src
46      - const: gcc_camera_ahb
47      - const: gcc_camera_axi
48      - const: slow_ahb_src
49      - const: soc_ahb
50      - const: vfe0_axi
51      - const: vfe0
52      - const: vfe0_cphy_rx
53      - const: vfe0_src
54      - const: vfe1_axi
55      - const: vfe1
56      - const: vfe1_cphy_rx
57      - const: vfe1_src
58      - const: vfe_lite
59      - const: vfe_lite_cphy_rx
60      - const: vfe_lite_src
61
62  interrupts:
63    minItems: 10
64    maxItems: 10
65
66  interrupt-names:
67    items:
68      - const: csid0
69      - const: csid1
70      - const: csid2
71      - const: csiphy0
72      - const: csiphy1
73      - const: csiphy2
74      - const: csiphy3
75      - const: vfe0
76      - const: vfe1
77      - const: vfe_lite
78
79  iommus:
80    maxItems: 4
81
82  power-domains:
83    items:
84      - description: IFE0 GDSC - Image Front End, Global Distributed Switch Controller.
85      - description: IFE1 GDSC - Image Front End, Global Distributed Switch Controller.
86      - description: Titan GDSC - Titan ISP Block, Global Distributed Switch Controller.
87
88  ports:
89    $ref: /schemas/graph.yaml#/properties/ports
90
91    description:
92      CSI input ports.
93
94    properties:
95      port@0:
96        $ref: /schemas/graph.yaml#/$defs/port-base
97        unevaluatedProperties: false
98        description:
99          Input port for receiving CSI data.
100
101        properties:
102          endpoint:
103            $ref: video-interfaces.yaml#
104            unevaluatedProperties: false
105
106            properties:
107              data-lanes:
108                minItems: 1
109                maxItems: 4
110
111              bus-type:
112                enum:
113                  - 1 # MEDIA_BUS_TYPE_CSI2_CPHY
114                  - 4 # MEDIA_BUS_TYPE_CSI2_DPHY
115
116            required:
117              - data-lanes
118
119      port@1:
120        $ref: /schemas/graph.yaml#/$defs/port-base
121        unevaluatedProperties: false
122        description:
123          Input port for receiving CSI data.
124
125        properties:
126          endpoint:
127            $ref: video-interfaces.yaml#
128            unevaluatedProperties: false
129
130            properties:
131              data-lanes:
132                minItems: 1
133                maxItems: 4
134
135              bus-type:
136                enum:
137                  - 1 # MEDIA_BUS_TYPE_CSI2_CPHY
138                  - 4 # MEDIA_BUS_TYPE_CSI2_DPHY
139
140            required:
141              - data-lanes
142
143      port@2:
144        $ref: /schemas/graph.yaml#/$defs/port-base
145        unevaluatedProperties: false
146        description:
147          Input port for receiving CSI data.
148
149        properties:
150          endpoint:
151            $ref: video-interfaces.yaml#
152            unevaluatedProperties: false
153
154            properties:
155              data-lanes:
156                minItems: 1
157                maxItems: 4
158
159              bus-type:
160                enum:
161                  - 1 # MEDIA_BUS_TYPE_CSI2_CPHY
162                  - 4 # MEDIA_BUS_TYPE_CSI2_DPHY
163
164            required:
165              - data-lanes
166
167      port@3:
168        $ref: /schemas/graph.yaml#/$defs/port-base
169        unevaluatedProperties: false
170        description:
171          Input port for receiving CSI data.
172
173        properties:
174          endpoint:
175            $ref: video-interfaces.yaml#
176            unevaluatedProperties: false
177
178            properties:
179              data-lanes:
180                minItems: 1
181                maxItems: 4
182
183              bus-type:
184                enum:
185                  - 1 # MEDIA_BUS_TYPE_CSI2_CPHY
186                  - 4 # MEDIA_BUS_TYPE_CSI2_DPHY
187
188            required:
189              - data-lanes
190
191  reg:
192    minItems: 10
193    maxItems: 10
194
195  reg-names:
196    items:
197      - const: csid0
198      - const: csid1
199      - const: csid2
200      - const: csiphy0
201      - const: csiphy1
202      - const: csiphy2
203      - const: csiphy3
204      - const: vfe0
205      - const: vfe1
206      - const: vfe_lite
207
208  vdda-phy-supply:
209    description:
210      Phandle to a regulator supply to PHY core block.
211
212  vdda-pll-supply:
213    description:
214      Phandle to 1.8V regulator supply to PHY refclk pll block.
215
216required:
217  - clock-names
218  - clocks
219  - compatible
220  - interrupt-names
221  - interrupts
222  - iommus
223  - power-domains
224  - reg
225  - reg-names
226  - vdda-phy-supply
227  - vdda-pll-supply
228
229additionalProperties: false
230
231examples:
232  - |
233    #include <dt-bindings/interrupt-controller/arm-gic.h>
234    #include <dt-bindings/clock/qcom,camcc-sdm845.h>
235    #include <dt-bindings/clock/qcom,gcc-sdm845.h>
236
237    soc {
238      #address-cells = <2>;
239      #size-cells = <2>;
240
241      camss: camss@acb3000 {
242        compatible = "qcom,sdm845-camss";
243
244        clocks = <&clock_camcc CAM_CC_CAMNOC_AXI_CLK>,
245          <&clock_camcc CAM_CC_CPAS_AHB_CLK>,
246          <&clock_camcc CAM_CC_CPHY_RX_CLK_SRC>,
247          <&clock_camcc CAM_CC_IFE_0_CSID_CLK>,
248          <&clock_camcc CAM_CC_IFE_0_CSID_CLK_SRC>,
249          <&clock_camcc CAM_CC_IFE_1_CSID_CLK>,
250          <&clock_camcc CAM_CC_IFE_1_CSID_CLK_SRC>,
251          <&clock_camcc CAM_CC_IFE_LITE_CSID_CLK>,
252          <&clock_camcc CAM_CC_IFE_LITE_CSID_CLK_SRC>,
253          <&clock_camcc CAM_CC_CSIPHY0_CLK>,
254          <&clock_camcc CAM_CC_CSI0PHYTIMER_CLK>,
255          <&clock_camcc CAM_CC_CSI0PHYTIMER_CLK_SRC>,
256          <&clock_camcc CAM_CC_CSIPHY1_CLK>,
257          <&clock_camcc CAM_CC_CSI1PHYTIMER_CLK>,
258          <&clock_camcc CAM_CC_CSI1PHYTIMER_CLK_SRC>,
259          <&clock_camcc CAM_CC_CSIPHY2_CLK>,
260          <&clock_camcc CAM_CC_CSI2PHYTIMER_CLK>,
261          <&clock_camcc CAM_CC_CSI2PHYTIMER_CLK_SRC>,
262          <&clock_camcc CAM_CC_CSIPHY3_CLK>,
263          <&clock_camcc CAM_CC_CSI3PHYTIMER_CLK>,
264          <&clock_camcc CAM_CC_CSI3PHYTIMER_CLK_SRC>,
265          <&gcc GCC_CAMERA_AHB_CLK>,
266          <&gcc GCC_CAMERA_AXI_CLK>,
267          <&clock_camcc CAM_CC_SLOW_AHB_CLK_SRC>,
268          <&clock_camcc CAM_CC_SOC_AHB_CLK>,
269          <&clock_camcc CAM_CC_IFE_0_AXI_CLK>,
270          <&clock_camcc CAM_CC_IFE_0_CLK>,
271          <&clock_camcc CAM_CC_IFE_0_CPHY_RX_CLK>,
272          <&clock_camcc CAM_CC_IFE_0_CLK_SRC>,
273          <&clock_camcc CAM_CC_IFE_1_AXI_CLK>,
274          <&clock_camcc CAM_CC_IFE_1_CLK>,
275          <&clock_camcc CAM_CC_IFE_1_CPHY_RX_CLK>,
276          <&clock_camcc CAM_CC_IFE_1_CLK_SRC>,
277          <&clock_camcc CAM_CC_IFE_LITE_CLK>,
278          <&clock_camcc CAM_CC_IFE_LITE_CPHY_RX_CLK>,
279          <&clock_camcc CAM_CC_IFE_LITE_CLK_SRC>;
280
281        clock-names = "camnoc_axi",
282          "cpas_ahb",
283          "cphy_rx_src",
284          "csi0",
285          "csi0_src",
286          "csi1",
287          "csi1_src",
288          "csi2",
289          "csi2_src",
290          "csiphy0",
291          "csiphy0_timer",
292          "csiphy0_timer_src",
293          "csiphy1",
294          "csiphy1_timer",
295          "csiphy1_timer_src",
296          "csiphy2",
297          "csiphy2_timer",
298          "csiphy2_timer_src",
299          "csiphy3",
300          "csiphy3_timer",
301          "csiphy3_timer_src",
302          "gcc_camera_ahb",
303          "gcc_camera_axi",
304          "slow_ahb_src",
305          "soc_ahb",
306          "vfe0_axi",
307          "vfe0",
308          "vfe0_cphy_rx",
309          "vfe0_src",
310          "vfe1_axi",
311          "vfe1",
312          "vfe1_cphy_rx",
313          "vfe1_src",
314          "vfe_lite",
315          "vfe_lite_cphy_rx",
316          "vfe_lite_src";
317
318        interrupts = <GIC_SPI 464 IRQ_TYPE_EDGE_RISING>,
319          <GIC_SPI 466 IRQ_TYPE_EDGE_RISING>,
320          <GIC_SPI 468 IRQ_TYPE_EDGE_RISING>,
321          <GIC_SPI 477 IRQ_TYPE_EDGE_RISING>,
322          <GIC_SPI 478 IRQ_TYPE_EDGE_RISING>,
323          <GIC_SPI 479 IRQ_TYPE_EDGE_RISING>,
324          <GIC_SPI 448 IRQ_TYPE_EDGE_RISING>,
325          <GIC_SPI 465 IRQ_TYPE_EDGE_RISING>,
326          <GIC_SPI 467 IRQ_TYPE_EDGE_RISING>,
327          <GIC_SPI 469 IRQ_TYPE_EDGE_RISING>;
328
329        interrupt-names = "csid0",
330          "csid1",
331          "csid2",
332          "csiphy0",
333          "csiphy1",
334          "csiphy2",
335          "csiphy3",
336          "vfe0",
337          "vfe1",
338          "vfe_lite";
339
340        iommus = <&apps_smmu 0x0808 0x0>,
341          <&apps_smmu 0x0810 0x8>,
342          <&apps_smmu 0x0c08 0x0>,
343          <&apps_smmu 0x0c10 0x8>;
344
345        power-domains = <&clock_camcc IFE_0_GDSC>,
346          <&clock_camcc IFE_1_GDSC>,
347          <&clock_camcc TITAN_TOP_GDSC>;
348
349        reg = <0 0xacb3000 0 0x1000>,
350          <0 0xacba000 0 0x1000>,
351          <0 0xacc8000 0 0x1000>,
352          <0 0xac65000 0 0x1000>,
353          <0 0xac66000 0 0x1000>,
354          <0 0xac67000 0 0x1000>,
355          <0 0xac68000 0 0x1000>,
356          <0 0xacaf000 0 0x4000>,
357          <0 0xacb6000 0 0x4000>,
358          <0 0xacc4000 0 0x4000>;
359
360        reg-names = "csid0",
361          "csid1",
362          "csid2",
363          "csiphy0",
364          "csiphy1",
365          "csiphy2",
366          "csiphy3",
367          "vfe0",
368          "vfe1",
369          "vfe_lite";
370
371        vdda-phy-supply = <&vreg_l1a_0p875>;
372        vdda-pll-supply = <&vreg_l26a_1p2>;
373
374        ports {
375          #address-cells = <1>;
376          #size-cells = <0>;
377        };
378      };
379    };
380