1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/media/nxp,imx8-isi.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: i.MX8 Image Sensing Interface 8 9maintainers: 10 - Laurent Pinchart <laurent.pinchart@ideasonboard.com> 11 12description: | 13 The Image Sensing Interface (ISI) combines image processing pipelines with 14 DMA engines to process and capture frames originating from a variety of 15 sources. The inputs to the ISI go through Pixel Link interfaces, and their 16 number and nature is SoC-dependent. They cover both capture interfaces (MIPI 17 CSI-2 RX, HDMI RX, ...) and display engine outputs for writeback support. 18 19properties: 20 compatible: 21 enum: 22 - fsl,imx8mn-isi 23 - fsl,imx8mp-isi 24 25 reg: 26 maxItems: 1 27 28 clocks: 29 items: 30 - description: The AXI clock 31 - description: The APB clock 32 # TODO: Check if the per-channel ipg_proc_clk clocks need to be specified 33 # as well, in case some SoCs have the ability to control them separately. 34 # This may be the case of the i.MX8[DQ]X(P) 35 36 clock-names: 37 items: 38 - const: axi 39 - const: apb 40 41 fsl,blk-ctrl: 42 $ref: /schemas/types.yaml#/definitions/phandle 43 description: 44 A phandle referencing the block control that contains the CSIS to ISI 45 gasket. 46 47 interrupts: 48 description: Processing pipeline interrupts, one per pipeline 49 minItems: 1 50 maxItems: 2 51 52 power-domains: 53 maxItems: 1 54 55 ports: 56 $ref: /schemas/graph.yaml#/properties/ports 57 description: | 58 Ports represent the Pixel Link inputs to the ISI. Their number and 59 assignment are model-dependent. Each port shall have a single endpoint. 60 61required: 62 - compatible 63 - reg 64 - interrupts 65 - clocks 66 - clock-names 67 - fsl,blk-ctrl 68 - ports 69 70allOf: 71 - if: 72 properties: 73 compatible: 74 contains: 75 const: fsl,imx8mn-isi 76 then: 77 properties: 78 interrupts: 79 maxItems: 1 80 ports: 81 properties: 82 port@0: 83 description: MIPI CSI-2 RX 84 required: 85 - port@0 86 87 - if: 88 properties: 89 compatible: 90 contains: 91 const: fsl,imx8mp-isi 92 then: 93 properties: 94 interrupts: 95 maxItems: 2 96 ports: 97 properties: 98 port@0: 99 description: MIPI CSI-2 RX 0 100 port@1: 101 description: MIPI CSI-2 RX 1 102 required: 103 - port@0 104 - port@1 105 106additionalProperties: false 107 108examples: 109 - | 110 #include <dt-bindings/clock/imx8mn-clock.h> 111 #include <dt-bindings/interrupt-controller/arm-gic.h> 112 #include <dt-bindings/interrupt-controller/irq.h> 113 #include <dt-bindings/power/imx8mn-power.h> 114 115 isi@32e20000 { 116 compatible = "fsl,imx8mn-isi"; 117 reg = <0x32e20000 0x100>; 118 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; 119 clocks = <&clk IMX8MN_CLK_DISP_AXI_ROOT>, 120 <&clk IMX8MN_CLK_DISP_APB_ROOT>; 121 clock-names = "axi", "apb"; 122 fsl,blk-ctrl = <&disp_blk_ctrl>; 123 power-domains = <&disp_blk_ctrl IMX8MN_DISPBLK_PD_ISI>; 124 125 ports { 126 #address-cells = <1>; 127 #size-cells = <0>; 128 129 port@0 { 130 reg = <0>; 131 isi_in: endpoint { 132 remote-endpoint = <&mipi_csi_out>; 133 }; 134 }; 135 }; 136 }; 137 138 - | 139 #include <dt-bindings/clock/imx8mp-clock.h> 140 #include <dt-bindings/interrupt-controller/arm-gic.h> 141 #include <dt-bindings/interrupt-controller/irq.h> 142 143 isi@32e00000 { 144 compatible = "fsl,imx8mp-isi"; 145 reg = <0x32e00000 0x4000>; 146 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>, 147 <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>; 148 clocks = <&clk IMX8MP_CLK_MEDIA_AXI_ROOT>, 149 <&clk IMX8MP_CLK_MEDIA_APB_ROOT>; 150 clock-names = "axi", "apb"; 151 fsl,blk-ctrl = <&media_blk_ctrl>; 152 power-domains = <&mediamix_pd>; 153 154 ports { 155 #address-cells = <1>; 156 #size-cells = <0>; 157 158 port@0 { 159 reg = <0>; 160 isi_in_0: endpoint { 161 remote-endpoint = <&mipi_csi_0_out>; 162 }; 163 }; 164 165 port@1 { 166 reg = <1>; 167 isi_in_1: endpoint { 168 remote-endpoint = <&mipi_csi_1_out>; 169 }; 170 }; 171 }; 172 }; 173... 174