xref: /freebsd/sys/contrib/device-tree/Bindings/media/nxp,imx7-mipi-csi2.yaml (revision 13ec1e3155c7e9bf037b12af186351b7fa9b9450) 
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/media/nxp,imx7-mipi-csi2.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: NXP i.MX7 MIPI CSI-2 receiver
8
9maintainers:
10  - Rui Miguel Silva <rmfrfs@gmail.com>
11
12description: |-
13  The NXP i.MX7 SoC family includes a MIPI CSI-2 receiver IP core, documented
14  as "CSIS V3.3". The IP core seems to originate from Samsung, and may be
15  compatible with some of the Exynos4 ad S5P SoCs.
16
17  While the CSI-2 receiver is separate from the MIPI D-PHY IP core, the PHY is
18  completely wrapped by the CSIS and doesn't expose a control interface of its
19  own. This binding thus covers both IP cores.
20
21properties:
22  compatible:
23    const: fsl,imx7-mipi-csi2
24
25  reg:
26    maxItems: 1
27
28  interrupts:
29    maxItems: 1
30
31  clocks:
32    items:
33      - description: The peripheral clock (a.k.a. APB clock)
34      - description: The external clock (optionally used as the pixel clock)
35      - description: The MIPI D-PHY clock
36
37  clock-names:
38    items:
39      - const: pclk
40      - const: wrap
41      - const: phy
42
43  power-domains:
44    maxItems: 1
45
46  phy-supply:
47    description: The MIPI D-PHY digital power supply
48
49  resets:
50    items:
51      - description: MIPI D-PHY slave reset
52
53  clock-frequency:
54    description: The desired external clock ("wrap") frequency, in Hz
55    default: 166000000
56
57  ports:
58    $ref: /schemas/graph.yaml#/properties/ports
59
60    properties:
61      port@0:
62        $ref: /schemas/graph.yaml#/$defs/port-base
63        unevaluatedProperties: false
64        description:
65          Input port node, single endpoint describing the CSI-2 transmitter.
66
67        properties:
68          endpoint:
69            $ref: video-interfaces.yaml#
70            unevaluatedProperties: false
71
72            properties:
73              data-lanes:
74                oneOf:
75                  - items:
76                      - const: 1
77                  - items:
78                      - const: 1
79                      - const: 2
80
81            required:
82              - data-lanes
83
84      port@1:
85        $ref: /schemas/graph.yaml#/properties/port
86        description:
87          Output port node
88
89required:
90  - compatible
91  - reg
92  - interrupts
93  - clocks
94  - clock-names
95  - power-domains
96  - phy-supply
97  - resets
98  - ports
99
100additionalProperties: false
101
102examples:
103  - |
104    #include <dt-bindings/clock/imx7d-clock.h>
105    #include <dt-bindings/interrupt-controller/arm-gic.h>
106    #include <dt-bindings/interrupt-controller/irq.h>
107    #include <dt-bindings/reset/imx7-reset.h>
108
109    mipi_csi: mipi-csi@30750000 {
110        compatible = "fsl,imx7-mipi-csi2";
111        reg = <0x30750000 0x10000>;
112        interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
113
114        clocks = <&clks IMX7D_IPG_ROOT_CLK>,
115                 <&clks IMX7D_MIPI_CSI_ROOT_CLK>,
116                 <&clks IMX7D_MIPI_DPHY_ROOT_CLK>;
117        clock-names = "pclk", "wrap", "phy";
118        clock-frequency = <166000000>;
119
120        power-domains = <&pgc_mipi_phy>;
121        phy-supply = <&reg_1p0d>;
122        resets = <&src IMX7_RESET_MIPI_PHY_MRST>;
123
124        ports {
125            #address-cells = <1>;
126            #size-cells = <0>;
127
128            port@0 {
129                reg = <0>;
130
131                mipi_from_sensor: endpoint {
132                    remote-endpoint = <&ov2680_to_mipi>;
133                    data-lanes = <1>;
134                };
135            };
136
137            port@1 {
138                reg = <1>;
139
140                mipi_vc0_to_csi_mux: endpoint {
141                    remote-endpoint = <&csi_mux_from_mipi_vc0>;
142                };
143            };
144        };
145    };
146
147...
148