1* Mediatek Media Data Path 2 3Media Data Path is used for scaling and color space conversion. 4 5Required properties (controller node): 6- compatible: "mediatek,mt8173-mdp" 7- mediatek,vpu: the node of video processor unit, see 8 Documentation/devicetree/bindings/media/mediatek-vpu.txt for details. 9 10Required properties (all function blocks, child node): 11- compatible: Should be one of 12 "mediatek,mt8173-mdp-rdma" - read DMA 13 "mediatek,mt8173-mdp-rsz" - resizer 14 "mediatek,mt8173-mdp-wdma" - write DMA 15 "mediatek,mt8173-mdp-wrot" - write DMA with rotation 16- reg: Physical base address and length of the function block register space 17- clocks: device clocks, see 18 Documentation/devicetree/bindings/clock/clock-bindings.txt for details. 19- power-domains: a phandle to the power domain, see 20 Documentation/devicetree/bindings/power/power_domain.txt for details. 21 22Required properties (DMA function blocks, child node): 23- compatible: Should be one of 24 "mediatek,mt8173-mdp-rdma" 25 "mediatek,mt8173-mdp-wdma" 26 "mediatek,mt8173-mdp-wrot" 27- iommus: should point to the respective IOMMU block with master port as 28 argument, see Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml 29 for details. 30 31Example: 32 mdp_rdma0: rdma@14001000 { 33 compatible = "mediatek,mt8173-mdp-rdma"; 34 "mediatek,mt8173-mdp"; 35 reg = <0 0x14001000 0 0x1000>; 36 clocks = <&mmsys CLK_MM_MDP_RDMA0>, 37 <&mmsys CLK_MM_MUTEX_32K>; 38 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 39 iommus = <&iommu M4U_PORT_MDP_RDMA0>; 40 mediatek,vpu = <&vpu>; 41 }; 42 43 mdp_rdma1: rdma@14002000 { 44 compatible = "mediatek,mt8173-mdp-rdma"; 45 reg = <0 0x14002000 0 0x1000>; 46 clocks = <&mmsys CLK_MM_MDP_RDMA1>, 47 <&mmsys CLK_MM_MUTEX_32K>; 48 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 49 iommus = <&iommu M4U_PORT_MDP_RDMA1>; 50 }; 51 52 mdp_rsz0: rsz@14003000 { 53 compatible = "mediatek,mt8173-mdp-rsz"; 54 reg = <0 0x14003000 0 0x1000>; 55 clocks = <&mmsys CLK_MM_MDP_RSZ0>; 56 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 57 }; 58 59 mdp_rsz1: rsz@14004000 { 60 compatible = "mediatek,mt8173-mdp-rsz"; 61 reg = <0 0x14004000 0 0x1000>; 62 clocks = <&mmsys CLK_MM_MDP_RSZ1>; 63 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 64 }; 65 66 mdp_rsz2: rsz@14005000 { 67 compatible = "mediatek,mt8173-mdp-rsz"; 68 reg = <0 0x14005000 0 0x1000>; 69 clocks = <&mmsys CLK_MM_MDP_RSZ2>; 70 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 71 }; 72 73 mdp_wdma0: wdma@14006000 { 74 compatible = "mediatek,mt8173-mdp-wdma"; 75 reg = <0 0x14006000 0 0x1000>; 76 clocks = <&mmsys CLK_MM_MDP_WDMA>; 77 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 78 iommus = <&iommu M4U_PORT_MDP_WDMA>; 79 }; 80 81 mdp_wrot0: wrot@14007000 { 82 compatible = "mediatek,mt8173-mdp-wrot"; 83 reg = <0 0x14007000 0 0x1000>; 84 clocks = <&mmsys CLK_MM_MDP_WROT0>; 85 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 86 iommus = <&iommu M4U_PORT_MDP_WROT0>; 87 }; 88 89 mdp_wrot1: wrot@14008000 { 90 compatible = "mediatek,mt8173-mdp-wrot"; 91 reg = <0 0x14008000 0 0x1000>; 92 clocks = <&mmsys CLK_MM_MDP_WROT1>; 93 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 94 iommus = <&iommu M4U_PORT_MDP_WROT1>; 95 }; 96