1# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/media/mediatek-jpeg-encoder.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: MediaTek JPEG Encoder 8 9maintainers: 10 - Xia Jiang <xia.jiang@mediatek.com> 11 12description: |- 13 MediaTek JPEG Encoder is the JPEG encode hardware present in MediaTek SoCs 14 15properties: 16 compatible: 17 items: 18 - enum: 19 - mediatek,mt2701-jpgenc 20 - mediatek,mt8183-jpgenc 21 - mediatek,mt8186-jpgenc 22 - mediatek,mt8188-jpgenc 23 - const: mediatek,mtk-jpgenc 24 reg: 25 maxItems: 1 26 27 interrupts: 28 maxItems: 1 29 30 clocks: 31 maxItems: 1 32 33 clock-names: 34 items: 35 - const: jpgenc 36 37 power-domains: 38 maxItems: 1 39 40 iommus: 41 maxItems: 2 42 description: | 43 Points to the respective IOMMU block with master port as argument, see 44 Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml for details. 45 Ports are according to the HW. 46 47required: 48 - compatible 49 - reg 50 - interrupts 51 - clocks 52 - clock-names 53 - power-domains 54 - iommus 55 56additionalProperties: false 57 58examples: 59 - | 60 #include <dt-bindings/clock/mt2701-clk.h> 61 #include <dt-bindings/interrupt-controller/arm-gic.h> 62 #include <dt-bindings/memory/mt2701-larb-port.h> 63 #include <dt-bindings/power/mt2701-power.h> 64 jpegenc: jpegenc@1500a000 { 65 compatible = "mediatek,mt2701-jpgenc", 66 "mediatek,mtk-jpgenc"; 67 reg = <0x1500a000 0x1000>; 68 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_LOW>; 69 clocks = <&imgsys CLK_IMG_VENC>; 70 clock-names = "jpgenc"; 71 power-domains = <&scpsys MT2701_POWER_DOMAIN_ISP>; 72 iommus = <&iommu MT2701_M4U_PORT_JPGENC_RDMA>, 73 <&iommu MT2701_M4U_PORT_JPGENC_BSDMA>; 74 }; 75