1# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/media/mediatek-jpeg-decoder.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: MediaTek JPEG Decoder 8 9maintainers: 10 - Xia Jiang <xia.jiang@mediatek.com> 11 12description: |- 13 Mediatek JPEG Decoder is the JPEG decode hardware present in Mediatek SoCs 14 15properties: 16 compatible: 17 oneOf: 18 - items: 19 - enum: 20 - mediatek,mt8173-jpgdec 21 - mediatek,mt2701-jpgdec 22 - items: 23 - enum: 24 - mediatek,mt7623-jpgdec 25 - const: mediatek,mt2701-jpgdec 26 27 reg: 28 maxItems: 1 29 30 interrupts: 31 maxItems: 1 32 33 clocks: 34 maxItems: 2 35 minItems: 2 36 37 clock-names: 38 items: 39 - const: jpgdec-smi 40 - const: jpgdec 41 42 power-domains: 43 maxItems: 1 44 45 iommus: 46 maxItems: 2 47 description: | 48 Points to the respective IOMMU block with master port as argument, see 49 Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml for details. 50 Ports are according to the HW. 51 52required: 53 - compatible 54 - reg 55 - interrupts 56 - clocks 57 - clock-names 58 - power-domains 59 - iommus 60 61additionalProperties: false 62 63examples: 64 - | 65 #include <dt-bindings/clock/mt2701-clk.h> 66 #include <dt-bindings/interrupt-controller/arm-gic.h> 67 #include <dt-bindings/memory/mt2701-larb-port.h> 68 #include <dt-bindings/power/mt2701-power.h> 69 jpegdec: jpegdec@15004000 { 70 compatible = "mediatek,mt2701-jpgdec"; 71 reg = <0x15004000 0x1000>; 72 interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_LOW>; 73 clocks = <&imgsys CLK_IMG_JPGDEC_SMI>, 74 <&imgsys CLK_IMG_JPGDEC>; 75 clock-names = "jpgdec-smi", 76 "jpgdec"; 77 power-domains = <&scpsys MT2701_POWER_DOMAIN_ISP>; 78 iommus = <&iommu MT2701_M4U_PORT_JPGDEC_WDMA>, 79 <&iommu MT2701_M4U_PORT_JPGDEC_BSDMA>; 80 }; 81