1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2 3%YAML 1.2 4--- 5$id: "http://devicetree.org/schemas/media/mediatek,vcodec-subdev-decoder.yaml#" 6$schema: "http://devicetree.org/meta-schemas/core.yaml#" 7 8title: Mediatek Video Decode Accelerator With Multi Hardware 9 10maintainers: 11 - Yunfei Dong <yunfei.dong@mediatek.com> 12 13description: | 14 Mediatek Video Decode is the video decode hardware present in Mediatek 15 SoCs which supports high resolution decoding functionalities. Required 16 parent and child device node. 17 18 About the Decoder Hardware Block Diagram, please check below: 19 20 +---------------------------------+------------------------------------+ 21 | | | 22 | input -> lat HW -> lat buffer --|--> lat buffer -> core HW -> output | 23 | || | || | 24 +------------||-------------------+---------------------||-------------+ 25 lat workqueue | core workqueue <parent> 26 -------------||-----------------------------------------||------------------ 27 || || <child> 28 \/ <----------------HW index-------------->\/ 29 +------------------------------------------------------+ 30 | enable/disable | 31 | clk power irq iommu | 32 | (lat/lat soc/core0/core1) | 33 +------------------------------------------------------+ 34 35 As above, there are parent and child devices, child mean each hardware. The child device 36 controls the information of each hardware independent which include clk/power/irq. 37 38 There are two workqueues in parent device: lat workqueue and core workqueue. They are used 39 to lat and core hardware deocder. Lat workqueue need to get input bitstream and lat buffer, 40 then enable lat to decode, writing the result to lat buffer, dislabe hardware when lat decode 41 done. Core workqueue need to get lat buffer and output buffer, then enable core to decode, 42 writing the result to output buffer, disable hardware when core decode done. These two 43 hardwares will decode each frame cyclically. 44 45 For the smi common may not the same for each hardware, can't combine all hardware in one node, 46 or leading to iommu fault when access dram data. 47 48properties: 49 compatible: 50 const: mediatek,mt8192-vcodec-dec 51 52 reg: 53 maxItems: 1 54 55 iommus: 56 minItems: 1 57 maxItems: 32 58 description: | 59 List of the hardware port in respective IOMMU block for current Socs. 60 Refer to bindings/iommu/mediatek,iommu.yaml. 61 62 mediatek,scp: 63 $ref: /schemas/types.yaml#/definitions/phandle 64 description: | 65 The node of system control processor (SCP), using 66 the remoteproc & rpmsg framework. 67 68 dma-ranges: 69 maxItems: 1 70 description: | 71 Describes the physical address space of IOMMU maps to memory. 72 73 "#address-cells": 74 const: 2 75 76 "#size-cells": 77 const: 2 78 79 ranges: true 80 81# Required child node: 82patternProperties: 83 '^vcodec-lat@[0-9a-f]+$': 84 type: object 85 86 properties: 87 compatible: 88 const: mediatek,mtk-vcodec-lat 89 90 reg: 91 maxItems: 1 92 93 interrupts: 94 maxItems: 1 95 96 iommus: 97 minItems: 1 98 maxItems: 32 99 description: | 100 List of the hardware port in respective IOMMU block for current Socs. 101 Refer to bindings/iommu/mediatek,iommu.yaml. 102 103 clocks: 104 maxItems: 5 105 106 clock-names: 107 items: 108 - const: sel 109 - const: soc-vdec 110 - const: soc-lat 111 - const: vdec 112 - const: top 113 114 assigned-clocks: 115 maxItems: 1 116 117 assigned-clock-parents: 118 maxItems: 1 119 120 power-domains: 121 maxItems: 1 122 123 required: 124 - compatible 125 - reg 126 - interrupts 127 - iommus 128 - clocks 129 - clock-names 130 - assigned-clocks 131 - assigned-clock-parents 132 - power-domains 133 134 additionalProperties: false 135 136 '^vcodec-core@[0-9a-f]+$': 137 type: object 138 139 properties: 140 compatible: 141 const: mediatek,mtk-vcodec-core 142 143 reg: 144 maxItems: 1 145 146 interrupts: 147 maxItems: 1 148 149 iommus: 150 minItems: 1 151 maxItems: 32 152 description: | 153 List of the hardware port in respective IOMMU block for current Socs. 154 Refer to bindings/iommu/mediatek,iommu.yaml. 155 156 clocks: 157 maxItems: 5 158 159 clock-names: 160 items: 161 - const: sel 162 - const: soc-vdec 163 - const: soc-lat 164 - const: vdec 165 - const: top 166 167 assigned-clocks: 168 maxItems: 1 169 170 assigned-clock-parents: 171 maxItems: 1 172 173 power-domains: 174 maxItems: 1 175 176 required: 177 - compatible 178 - reg 179 - interrupts 180 - iommus 181 - clocks 182 - clock-names 183 - assigned-clocks 184 - assigned-clock-parents 185 - power-domains 186 187 additionalProperties: false 188 189required: 190 - compatible 191 - reg 192 - iommus 193 - mediatek,scp 194 - dma-ranges 195 - ranges 196 197additionalProperties: false 198 199examples: 200 - | 201 #include <dt-bindings/interrupt-controller/arm-gic.h> 202 #include <dt-bindings/memory/mt8192-larb-port.h> 203 #include <dt-bindings/interrupt-controller/irq.h> 204 #include <dt-bindings/clock/mt8192-clk.h> 205 #include <dt-bindings/power/mt8192-power.h> 206 207 bus@16000000 { 208 #address-cells = <2>; 209 #size-cells = <2>; 210 ranges = <0 0x16000000 0x16000000 0 0x40000>; 211 212 video-codec@16000000 { 213 compatible = "mediatek,mt8192-vcodec-dec"; 214 mediatek,scp = <&scp>; 215 iommus = <&iommu0 M4U_PORT_L4_VDEC_MC_EXT>; 216 dma-ranges = <0x1 0x0 0x0 0x40000000 0x0 0xfff00000>; 217 #address-cells = <2>; 218 #size-cells = <2>; 219 ranges = <0 0 0 0x16000000 0 0x40000>; 220 reg = <0 0x16000000 0 0x1000>; /* VDEC_SYS */ 221 vcodec-lat@10000 { 222 compatible = "mediatek,mtk-vcodec-lat"; 223 reg = <0 0x10000 0 0x800>; 224 interrupts = <GIC_SPI 426 IRQ_TYPE_LEVEL_HIGH 0>; 225 iommus = <&iommu0 M4U_PORT_L5_VDEC_LAT0_VLD_EXT>, 226 <&iommu0 M4U_PORT_L5_VDEC_LAT0_VLD2_EXT>, 227 <&iommu0 M4U_PORT_L5_VDEC_LAT0_AVC_MV_EXT>, 228 <&iommu0 M4U_PORT_L5_VDEC_LAT0_PRED_RD_EXT>, 229 <&iommu0 M4U_PORT_L5_VDEC_LAT0_TILE_EXT>, 230 <&iommu0 M4U_PORT_L5_VDEC_LAT0_WDMA_EXT>, 231 <&iommu0 M4U_PORT_L5_VDEC_LAT0_RG_CTRL_DMA_EXT>, 232 <&iommu0 M4U_PORT_L5_VDEC_UFO_ENC_EXT>; 233 clocks = <&topckgen CLK_TOP_VDEC_SEL>, 234 <&vdecsys_soc CLK_VDEC_SOC_VDEC>, 235 <&vdecsys_soc CLK_VDEC_SOC_LAT>, 236 <&vdecsys_soc CLK_VDEC_SOC_LARB1>, 237 <&topckgen CLK_TOP_MAINPLL_D4>; 238 clock-names = "sel", "soc-vdec", "soc-lat", "vdec", "top"; 239 assigned-clocks = <&topckgen CLK_TOP_VDEC_SEL>; 240 assigned-clock-parents = <&topckgen CLK_TOP_MAINPLL_D4>; 241 power-domains = <&spm MT8192_POWER_DOMAIN_VDEC>; 242 }; 243 244 vcodec-core@25000 { 245 compatible = "mediatek,mtk-vcodec-core"; 246 reg = <0 0x25000 0 0x1000>; 247 interrupts = <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH 0>; 248 iommus = <&iommu0 M4U_PORT_L4_VDEC_MC_EXT>, 249 <&iommu0 M4U_PORT_L4_VDEC_UFO_EXT>, 250 <&iommu0 M4U_PORT_L4_VDEC_PP_EXT>, 251 <&iommu0 M4U_PORT_L4_VDEC_PRED_RD_EXT>, 252 <&iommu0 M4U_PORT_L4_VDEC_PRED_WR_EXT>, 253 <&iommu0 M4U_PORT_L4_VDEC_PPWRAP_EXT>, 254 <&iommu0 M4U_PORT_L4_VDEC_TILE_EXT>, 255 <&iommu0 M4U_PORT_L4_VDEC_VLD_EXT>, 256 <&iommu0 M4U_PORT_L4_VDEC_VLD2_EXT>, 257 <&iommu0 M4U_PORT_L4_VDEC_AVC_MV_EXT>, 258 <&iommu0 M4U_PORT_L4_VDEC_RG_CTRL_DMA_EXT>; 259 clocks = <&topckgen CLK_TOP_VDEC_SEL>, 260 <&vdecsys CLK_VDEC_VDEC>, 261 <&vdecsys CLK_VDEC_LAT>, 262 <&vdecsys CLK_VDEC_LARB1>, 263 <&topckgen CLK_TOP_MAINPLL_D4>; 264 clock-names = "sel", "soc-vdec", "soc-lat", "vdec", "top"; 265 assigned-clocks = <&topckgen CLK_TOP_VDEC_SEL>; 266 assigned-clock-parents = <&topckgen CLK_TOP_MAINPLL_D4>; 267 power-domains = <&spm MT8192_POWER_DOMAIN_VDEC2>; 268 }; 269 }; 270 }; 271