xref: /freebsd/sys/contrib/device-tree/Bindings/media/mediatek,vcodec-encoder.yaml (revision b197d4b893974c9eb4d7b38704c6d5c486235d6f) 
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2
3%YAML 1.2
4---
5$id: http://devicetree.org/schemas/media/mediatek,vcodec-encoder.yaml#
6$schema: http://devicetree.org/meta-schemas/core.yaml#
7
8title: Mediatek Video Encode Accelerator
9
10maintainers:
11  - Yunfei Dong <yunfei.dong@mediatek.com>
12
13description: |+
14  Mediatek Video Encode is the video encode hardware present in Mediatek
15  SoCs which supports high resolution encoding functionalities.
16
17properties:
18  compatible:
19    enum:
20      - mediatek,mt8173-vcodec-enc-vp8
21      - mediatek,mt8173-vcodec-enc
22      - mediatek,mt8183-vcodec-enc
23      - mediatek,mt8192-vcodec-enc
24      - mediatek,mt8195-vcodec-enc
25
26  reg:
27    maxItems: 1
28
29  interrupts:
30    maxItems: 1
31
32  clocks:
33    minItems: 1
34    maxItems: 5
35
36  clock-names:
37    minItems: 1
38    maxItems: 5
39
40  assigned-clocks: true
41
42  assigned-clock-parents: true
43
44  iommus:
45    minItems: 1
46    maxItems: 32
47    description: |
48      List of the hardware port in respective IOMMU block for current Socs.
49      Refer to bindings/iommu/mediatek,iommu.yaml.
50
51  dma-ranges:
52    maxItems: 1
53    description: |
54      Describes the physical address space of IOMMU maps to memory.
55
56  mediatek,vpu:
57    $ref: /schemas/types.yaml#/definitions/phandle
58    description:
59      Describes point to vpu.
60
61  mediatek,scp:
62    $ref: /schemas/types.yaml#/definitions/phandle
63    description:
64      Describes point to scp.
65
66required:
67  - compatible
68  - reg
69  - interrupts
70  - clocks
71  - clock-names
72  - iommus
73  - assigned-clocks
74  - assigned-clock-parents
75
76allOf:
77  - if:
78      properties:
79        compatible:
80          contains:
81            enum:
82              - mediatek,mt8183-vcodec-enc
83              - mediatek,mt8192-vcodec-enc
84
85    then:
86      required:
87        - mediatek,scp
88
89  - if:
90      properties:
91        compatible:
92          contains:
93            enum:
94              - mediatek,mt8173-vcodec-enc-vp8
95              - mediatek,mt8173-vcodec-enc
96
97    then:
98      required:
99        - mediatek,vpu
100
101  - if:
102      properties:
103        compatible:
104          enum:
105            - mediatek,mt8173-vcodec-enc
106            - mediatek,mt8192-vcodec-enc
107
108    then:
109      properties:
110        clock:
111          items:
112            minItems: 1
113            maxItems: 1
114        clock-names:
115          items:
116            - const: venc_sel
117    else:  # for vp8 hw decoder
118      properties:
119        clock:
120          items:
121            minItems: 1
122            maxItems: 1
123        clock-names:
124          items:
125            - const: venc_lt_sel
126
127additionalProperties: false
128
129examples:
130  - |
131    #include <dt-bindings/interrupt-controller/arm-gic.h>
132    #include <dt-bindings/clock/mt8173-clk.h>
133    #include <dt-bindings/memory/mt8173-larb-port.h>
134    #include <dt-bindings/interrupt-controller/irq.h>
135
136    vcodec_enc_avc: vcodec@18002000 {
137      compatible = "mediatek,mt8173-vcodec-enc";
138      reg = <0x18002000 0x1000>;
139      interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_LOW>;
140      iommus = <&iommu M4U_PORT_VENC_RCPU>,
141             <&iommu M4U_PORT_VENC_REC>,
142             <&iommu M4U_PORT_VENC_BSDMA>,
143             <&iommu M4U_PORT_VENC_SV_COMV>,
144             <&iommu M4U_PORT_VENC_RD_COMV>,
145             <&iommu M4U_PORT_VENC_CUR_LUMA>,
146             <&iommu M4U_PORT_VENC_CUR_CHROMA>,
147             <&iommu M4U_PORT_VENC_REF_LUMA>,
148             <&iommu M4U_PORT_VENC_REF_CHROMA>,
149             <&iommu M4U_PORT_VENC_NBM_RDMA>,
150             <&iommu M4U_PORT_VENC_NBM_WDMA>;
151      mediatek,vpu = <&vpu>;
152      clocks = <&topckgen CLK_TOP_VENC_SEL>;
153      clock-names = "venc_sel";
154      assigned-clocks = <&topckgen CLK_TOP_VENC_SEL>;
155      assigned-clock-parents = <&topckgen CLK_TOP_VCODECPLL>;
156    };
157
158    vcodec_enc_vp8: vcodec@19002000 {
159      compatible = "mediatek,mt8173-vcodec-enc-vp8";
160      reg =  <0x19002000 0x1000>;	/* VENC_LT_SYS */
161      interrupts = <GIC_SPI 202 IRQ_TYPE_LEVEL_LOW>;
162      iommus = <&iommu M4U_PORT_VENC_RCPU_SET2>,
163             <&iommu M4U_PORT_VENC_REC_FRM_SET2>,
164             <&iommu M4U_PORT_VENC_BSDMA_SET2>,
165             <&iommu M4U_PORT_VENC_SV_COMA_SET2>,
166             <&iommu M4U_PORT_VENC_RD_COMA_SET2>,
167             <&iommu M4U_PORT_VENC_CUR_LUMA_SET2>,
168             <&iommu M4U_PORT_VENC_CUR_CHROMA_SET2>,
169             <&iommu M4U_PORT_VENC_REF_LUMA_SET2>,
170             <&iommu M4U_PORT_VENC_REC_CHROMA_SET2>;
171      mediatek,vpu = <&vpu>;
172      clocks = <&topckgen CLK_TOP_VENC_LT_SEL>;
173      clock-names = "venc_lt_sel";
174      assigned-clocks = <&topckgen CLK_TOP_VENC_LT_SEL>;
175      assigned-clock-parents = <&topckgen CLK_TOP_VCODECPLL_370P5>;
176    };
177