xref: /freebsd/sys/contrib/device-tree/Bindings/media/mediatek,mdp3-rsz.yaml (revision 9978553d0199e7ec0bdd1c44fc7f6c7b0c11e43b) 
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/media/mediatek,mdp3-rsz.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: MediaTek Resizer
8
9maintainers:
10  - Matthias Brugger <matthias.bgg@gmail.com>
11  - Moudy Ho <moudy.ho@mediatek.com>
12
13description: |
14  One of Media Data Path 3 (MDP3) components used to do frame resizing.
15
16properties:
17  compatible:
18    oneOf:
19      - enum:
20          - mediatek,mt8183-mdp3-rsz
21      - items:
22          - enum:
23              - mediatek,mt8188-mdp3-rsz
24              - mediatek,mt8195-mdp3-rsz
25          - const: mediatek,mt8183-mdp3-rsz
26
27  reg:
28    maxItems: 1
29
30  mediatek,gce-client-reg:
31    $ref: /schemas/types.yaml#/definitions/phandle-array
32    items:
33      items:
34        - description: phandle of GCE
35        - description: GCE subsys id
36        - description: register offset
37        - description: register size
38    description: The register of client driver can be configured by gce with
39      4 arguments defined in this property. Each GCE subsys id is mapping to
40      a client defined in the header include/dt-bindings/gce/<chip>-gce.h.
41
42  mediatek,gce-events:
43    description:
44      The event id which is mapping to the specific hardware event signal
45      to gce. The event id is defined in the gce header
46      include/dt-bindings/gce/<chip>-gce.h of each chips.
47    $ref: /schemas/types.yaml#/definitions/uint32-array
48
49  clocks:
50    minItems: 1
51
52required:
53  - compatible
54  - reg
55  - mediatek,gce-client-reg
56  - mediatek,gce-events
57  - clocks
58
59additionalProperties: false
60
61examples:
62  - |
63    #include <dt-bindings/clock/mt8183-clk.h>
64    #include <dt-bindings/gce/mt8183-gce.h>
65
66    mdp3_rsz0: mdp3-rsz0@14003000 {
67      compatible = "mediatek,mt8183-mdp3-rsz";
68      reg = <0x14003000 0x1000>;
69      mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x3000 0x1000>;
70      mediatek,gce-events = <CMDQ_EVENT_MDP_RSZ0_SOF>,
71                            <CMDQ_EVENT_MDP_RSZ0_EOF>;
72      clocks = <&mmsys CLK_MM_MDP_RSZ0>;
73    };
74
75    mdp3_rsz1: mdp3-rsz1@14004000 {
76      compatible = "mediatek,mt8183-mdp3-rsz";
77      reg = <0x14004000 0x1000>;
78      mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x4000 0x1000>;
79      mediatek,gce-events = <CMDQ_EVENT_MDP_RSZ1_SOF>,
80                            <CMDQ_EVENT_MDP_RSZ1_EOF>;
81      clocks = <&mmsys CLK_MM_MDP_RSZ1>;
82    };
83