xref: /freebsd/sys/contrib/device-tree/Bindings/media/mediatek,mdp3-rsz.yaml (revision 7fdf597e96a02165cfe22ff357b857d5fa15ed8a) 
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/media/mediatek,mdp3-rsz.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: MediaTek Resizer
8
9maintainers:
10  - Matthias Brugger <matthias.bgg@gmail.com>
11  - Moudy Ho <moudy.ho@mediatek.com>
12
13description: |
14  One of Media Data Path 3 (MDP3) components used to do frame resizing.
15
16properties:
17  compatible:
18    oneOf:
19      - enum:
20          - mediatek,mt8183-mdp3-rsz
21      - items:
22          - enum:
23              - mediatek,mt8195-mdp3-rsz
24          - const: mediatek,mt8183-mdp3-rsz
25
26  reg:
27    maxItems: 1
28
29  mediatek,gce-client-reg:
30    $ref: /schemas/types.yaml#/definitions/phandle-array
31    items:
32      items:
33        - description: phandle of GCE
34        - description: GCE subsys id
35        - description: register offset
36        - description: register size
37    description: The register of client driver can be configured by gce with
38      4 arguments defined in this property. Each GCE subsys id is mapping to
39      a client defined in the header include/dt-bindings/gce/<chip>-gce.h.
40
41  mediatek,gce-events:
42    description:
43      The event id which is mapping to the specific hardware event signal
44      to gce. The event id is defined in the gce header
45      include/dt-bindings/gce/<chip>-gce.h of each chips.
46    $ref: /schemas/types.yaml#/definitions/uint32-array
47
48  clocks:
49    minItems: 1
50
51required:
52  - compatible
53  - reg
54  - mediatek,gce-client-reg
55  - mediatek,gce-events
56  - clocks
57
58additionalProperties: false
59
60examples:
61  - |
62    #include <dt-bindings/clock/mt8183-clk.h>
63    #include <dt-bindings/gce/mt8183-gce.h>
64
65    mdp3_rsz0: mdp3-rsz0@14003000 {
66      compatible = "mediatek,mt8183-mdp3-rsz";
67      reg = <0x14003000 0x1000>;
68      mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x3000 0x1000>;
69      mediatek,gce-events = <CMDQ_EVENT_MDP_RSZ0_SOF>,
70                            <CMDQ_EVENT_MDP_RSZ0_EOF>;
71      clocks = <&mmsys CLK_MM_MDP_RSZ0>;
72    };
73
74    mdp3_rsz1: mdp3-rsz1@14004000 {
75      compatible = "mediatek,mt8183-mdp3-rsz";
76      reg = <0x14004000 0x1000>;
77      mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x4000 0x1000>;
78      mediatek,gce-events = <CMDQ_EVENT_MDP_RSZ1_SOF>,
79                            <CMDQ_EVENT_MDP_RSZ1_EOF>;
80      clocks = <&mmsys CLK_MM_MDP_RSZ1>;
81    };
82