xref: /freebsd/sys/contrib/device-tree/Bindings/media/imx7-mipi-csi2.txt (revision 59c8e88e72633afbc47a4ace0d2170d00d51f7dc) 
1Freescale i.MX7 Mipi CSI2
2=========================
3
4mipi_csi2 node
5--------------
6
7This is the device node for the MIPI CSI-2 receiver core in i.MX7 SoC. It is
8compatible with previous version of Samsung D-phy.
9
10Required properties:
11
12- compatible    : "fsl,imx7-mipi-csi2";
13- reg           : base address and length of the register set for the device;
14- interrupts    : should contain MIPI CSIS interrupt;
15- clocks        : list of clock specifiers, see
16        Documentation/devicetree/bindings/clock/clock-bindings.txt for details;
17- clock-names   : must contain "pclk", "wrap" and "phy" entries, matching
18                  entries in the clock property;
19- power-domains : a phandle to the power domain, see
20          Documentation/devicetree/bindings/power/power_domain.txt for details.
21- reset-names   : should include following entry "mrst";
22- resets        : a list of phandle, should contain reset entry of
23                  reset-names;
24- phy-supply    : from the generic phy bindings, a phandle to a regulator that
25	          provides power to MIPI CSIS core;
26
27Optional properties:
28
29- clock-frequency : The IP's main (system bus) clock frequency in Hz, default
30		    value when this property is not specified is 166 MHz;
31- fsl,csis-hs-settle : differential receiver (HS-RX) settle time;
32
33The device node should contain two 'port' child nodes with one child 'endpoint'
34node, according to the bindings defined in:
35 Documentation/devicetree/bindings/ media/video-interfaces.txt.
36 The following are properties specific to those nodes.
37
38port node
39---------
40
41- reg		  : (required) can take the values 0 or 1, where 0 shall be
42                     related to the sink port and port 1 shall be the source
43                     one;
44
45endpoint node
46-------------
47
48- data-lanes    : (required) an array specifying active physical MIPI-CSI2
49		    data input lanes and their mapping to logical lanes; this
50                    shall only be applied to port 0 (sink port), the array's
51                    content is unused only its length is meaningful,
52                    in this case the maximum length supported is 2;
53
54example:
55
56        mipi_csi: mipi-csi@30750000 {
57                #address-cells = <1>;
58                #size-cells = <0>;
59
60                compatible = "fsl,imx7-mipi-csi2";
61                reg = <0x30750000 0x10000>;
62                interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
63                clocks = <&clks IMX7D_IPG_ROOT_CLK>,
64                                <&clks IMX7D_MIPI_CSI_ROOT_CLK>,
65                                <&clks IMX7D_MIPI_DPHY_ROOT_CLK>;
66                clock-names = "pclk", "wrap", "phy";
67                clock-frequency = <166000000>;
68                power-domains = <&pgc_mipi_phy>;
69                phy-supply = <&reg_1p0d>;
70                resets = <&src IMX7_RESET_MIPI_PHY_MRST>;
71                reset-names = "mrst";
72                fsl,csis-hs-settle = <3>;
73
74                port@0 {
75                        reg = <0>;
76
77                        mipi_from_sensor: endpoint {
78                                remote-endpoint = <&ov2680_to_mipi>;
79                                data-lanes = <1>;
80                        };
81                };
82
83                port@1 {
84                        reg = <1>;
85
86                        mipi_vc0_to_csi_mux: endpoint {
87                                remote-endpoint = <&csi_mux_from_mipi_vc0>;
88                        };
89                };
90        };
91