xref: /freebsd/sys/contrib/device-tree/Bindings/media/cdns,csi2rx.yaml (revision 6580f5c38dd5b01aeeaed16b370f1a12423437f0) 
1# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/media/cdns,csi2rx.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Cadence MIPI-CSI2 RX controller
8
9maintainers:
10  - Maxime Ripard <mripard@kernel.org>
11
12description:
13  The Cadence MIPI-CSI2 RX controller is a CSI-2 bridge supporting up to 4 CSI
14  lanes in input, and 4 different pixel streams in output.
15
16properties:
17  compatible:
18    items:
19      - enum:
20          - starfive,jh7110-csi2rx
21          - ti,j721e-csi2rx
22      - const: cdns,csi2rx
23
24  reg:
25    maxItems: 1
26
27  clocks:
28    items:
29      - description: CSI2Rx system clock
30      - description: Gated Register bank clock for APB interface
31      - description: pixel Clock for Stream interface 0
32      - description: pixel Clock for Stream interface 1
33      - description: pixel Clock for Stream interface 2
34      - description: pixel Clock for Stream interface 3
35
36  clock-names:
37    items:
38      - const: sys_clk
39      - const: p_clk
40      - const: pixel_if0_clk
41      - const: pixel_if1_clk
42      - const: pixel_if2_clk
43      - const: pixel_if3_clk
44
45  resets:
46    items:
47      - description: CSI2Rx system reset
48      - description: Gated Register bank reset for APB interface
49      - description: pixel reset for Stream interface 0
50      - description: pixel reset for Stream interface 1
51      - description: pixel reset for Stream interface 2
52      - description: pixel reset for Stream interface 3
53
54  reset-names:
55    items:
56      - const: sys
57      - const: reg_bank
58      - const: pixel_if0
59      - const: pixel_if1
60      - const: pixel_if2
61      - const: pixel_if3
62
63  phys:
64    maxItems: 1
65    description: MIPI D-PHY
66
67  phy-names:
68    items:
69      - const: dphy
70
71  ports:
72    $ref: /schemas/graph.yaml#/properties/ports
73
74    properties:
75      port@0:
76        $ref: /schemas/graph.yaml#/$defs/port-base
77        unevaluatedProperties: false
78        description:
79          Input port node, single endpoint describing the CSI-2 transmitter.
80
81        properties:
82          endpoint:
83            $ref: video-interfaces.yaml#
84            unevaluatedProperties: false
85
86            properties:
87              bus-type:
88                const: 4
89
90              clock-lanes:
91                const: 0
92
93              data-lanes:
94                minItems: 1
95                maxItems: 4
96                items:
97                  maximum: 4
98
99            required:
100              - data-lanes
101
102      port@1:
103        $ref: /schemas/graph.yaml#/properties/port
104        description:
105          Stream 0 Output port node
106
107      port@2:
108        $ref: /schemas/graph.yaml#/properties/port
109        description:
110          Stream 1 Output port node
111
112      port@3:
113        $ref: /schemas/graph.yaml#/properties/port
114        description:
115          Stream 2 Output port node
116
117      port@4:
118        $ref: /schemas/graph.yaml#/properties/port
119        description:
120          Stream 3 Output port node
121
122    required:
123      - port@0
124
125required:
126  - compatible
127  - reg
128  - clocks
129  - clock-names
130  - ports
131
132additionalProperties: false
133
134examples:
135  - |
136    csi@d060000 {
137        compatible = "starfive,jh7110-csi2rx", "cdns,csi2rx";
138        reg = <0x0d060000 0x1000>;
139        clocks = <&byteclock 7>, <&byteclock 6>,
140                 <&coreclock 8>, <&coreclock 9>,
141                 <&coreclock 10>, <&coreclock 11>;
142        clock-names = "sys_clk", "p_clk",
143                      "pixel_if0_clk", "pixel_if1_clk",
144                      "pixel_if2_clk", "pixel_if3_clk";
145        resets = <&bytereset 9>, <&bytereset 4>,
146                 <&corereset 5>, <&corereset 6>,
147                 <&corereset 7>, <&corereset 8>;
148        reset-names = "sys", "reg_bank",
149                      "pixel_if0", "pixel_if1",
150                      "pixel_if2", "pixel_if3";
151        phys = <&csi_phy>;
152        phy-names = "dphy";
153
154        ports {
155                #address-cells = <1>;
156                #size-cells = <0>;
157
158                port@0 {
159                    reg = <0>;
160
161                    csi2rx_in_sensor: endpoint {
162                        remote-endpoint = <&sensor_out_csi2rx>;
163                        clock-lanes = <0>;
164                        data-lanes = <1 2>;
165                    };
166                };
167
168                port@1 {
169                    reg = <1>;
170
171                    csi2rx_out_grabber0: endpoint {
172                        remote-endpoint = <&grabber0_in_csi2rx>;
173                    };
174                };
175
176                port@2 {
177                    reg = <2>;
178
179                    csi2rx_out_grabber1: endpoint {
180                        remote-endpoint = <&grabber1_in_csi2rx>;
181                    };
182                };
183
184                port@3 {
185                    reg = <3>;
186
187                    csi2rx_out_grabber2: endpoint {
188                        remote-endpoint = <&grabber2_in_csi2rx>;
189                    };
190                };
191
192                port@4 {
193                    reg = <4>;
194
195                    csi2rx_out_grabber3: endpoint {
196                        remote-endpoint = <&grabber3_in_csi2rx>;
197                    };
198                };
199        };
200    };
201
202...
203