1Device-tree bindings for the Allegro DVT video IP codecs present in the Xilinx 2ZynqMP SoC. The IP core may either be a H.264/H.265 encoder or H.264/H.265 3decoder ip core. 4 5Each actual codec engines is controlled by a microcontroller (MCU). Host 6software uses a provided mailbox interface to communicate with the MCU. The 7MCU share an interrupt. 8 9Required properties: 10 - compatible: value should be one of the following 11 "allegro,al5e-1.1", "allegro,al5e": encoder IP core 12 "allegro,al5d-1.1", "allegro,al5d": decoder IP core 13 - reg: base and length of the memory mapped register region and base and 14 length of the memory mapped sram 15 - reg-names: must include "regs" and "sram" 16 - interrupts: shared interrupt from the MCUs to the processing system 17 - clocks: must contain an entry for each entry in clock-names 18 - clock-names: must include "core_clk", "mcu_clk", "m_axi_core_aclk", 19 "m_axi_mcu_aclk", "s_axi_lite_aclk" 20 21Example: 22 al5e: video-codec@a0009000 { 23 compatible = "allegro,al5e-1.1", "allegro,al5e"; 24 reg = <0 0xa0009000 0 0x1000>, 25 <0 0xa0000000 0 0x8000>; 26 reg-names = "regs", "sram"; 27 interrupts = <0 96 4>; 28 clocks = <&xlnx_vcu 0>, <&xlnx_vcu 1>, 29 <&clkc 71>, <&clkc 71>, <&clkc 71>; 30 clock-names = "core_clk", "mcu_clk", "m_axi_core_aclk", 31 "m_axi_mcu_aclk", "s_axi_lite_aclk" 32 }; 33 al5d: video-codec@a0029000 { 34 compatible = "allegro,al5d-1.1", "allegro,al5d"; 35 reg = <0 0xa0029000 0 0x1000>, 36 <0 0xa0020000 0 0x8000>; 37 reg-names = "regs", "sram"; 38 interrupts = <0 96 4>; 39 clocks = <&xlnx_vcu 2>, <&xlnx_vcu 3>, 40 <&clkc 71>, <&clkc 71>, <&clkc 71>; 41 clock-names = "core_clk", "mcu_clk", "m_axi_core_aclk", 42 "m_axi_mcu_aclk", "s_axi_lite_aclk" 43 }; 44