xref: /freebsd/sys/contrib/device-tree/Bindings/mailbox/qcom-ipcc.yaml (revision 5f4c09dd85bff675e0ca63c55ea3c517e0fddfcc) 
1# SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/mailbox/qcom-ipcc.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Qualcomm Technologies, Inc. Inter-Processor Communication Controller
8
9maintainers:
10  - Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
11
12description:
13  The Inter-Processor Communication Controller (IPCC) is a centralized hardware
14  to route interrupts across various subsystems. It involves a three-level
15  addressing scheme called protocol, client and signal. For example, consider an
16  entity on the Application Processor Subsystem (APSS) that wants to listen to
17  Modem's interrupts via Shared Memory Point to Point (SMP2P) interface. In such
18  a case, the client would be Modem (client-id is 2) and the signal would be
19  SMP2P (signal-id is 2). The SMP2P itself falls under the Multiprocessor (MPROC)
20  protocol (protocol-id is 0). Refer include/dt-bindings/mailbox/qcom-ipcc.h
21  for the list of such IDs.
22
23properties:
24  compatible:
25    items:
26      - enum:
27          - qcom,qdu1000-ipcc
28          - qcom,sa8775p-ipcc
29          - qcom,sc7280-ipcc
30          - qcom,sc8280xp-ipcc
31          - qcom,sm6350-ipcc
32          - qcom,sm6375-ipcc
33          - qcom,sm8250-ipcc
34          - qcom,sm8350-ipcc
35          - qcom,sm8450-ipcc
36          - qcom,sm8550-ipcc
37      - const: qcom,ipcc
38
39  reg:
40    maxItems: 1
41
42  interrupts:
43    maxItems: 1
44
45  interrupt-controller: true
46
47  "#interrupt-cells":
48    const: 3
49    description:
50      The first cell is the client-id, the second cell is the signal-id and the
51      third cell is the interrupt type.
52
53  "#mbox-cells":
54    const: 2
55    description:
56      The first cell is the client-id, and the second cell is the signal-id.
57
58required:
59  - compatible
60  - reg
61  - interrupts
62  - interrupt-controller
63  - "#interrupt-cells"
64  - "#mbox-cells"
65
66additionalProperties: false
67
68examples:
69  - |
70    #include <dt-bindings/interrupt-controller/arm-gic.h>
71    #include <dt-bindings/mailbox/qcom-ipcc.h>
72
73    mailbox@408000 {
74        compatible = "qcom,sm8250-ipcc", "qcom,ipcc";
75        reg = <0x408000 0x1000>;
76        interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>;
77        interrupt-controller;
78        #interrupt-cells = <3>;
79        #mbox-cells = <2>;
80    };
81