xref: /freebsd/sys/contrib/device-tree/Bindings/mailbox/qcom-ipcc.yaml (revision 31ba4ce8898f9dfa5e7f054fdbc26e50a599a6e3) 
1# SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/mailbox/qcom-ipcc.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Qualcomm Technologies, Inc. Inter-Processor Communication Controller
8
9maintainers:
10  - Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
11
12description:
13  The Inter-Processor Communication Controller (IPCC) is a centralized hardware
14  to route interrupts across various subsystems. It involves a three-level
15  addressing scheme called protocol, client and signal. For example, consider an
16  entity on the Application Processor Subsystem (APSS) that wants to listen to
17  Modem's interrupts via Shared Memory Point to Point (SMP2P) interface. In such
18  a case, the client would be Modem (client-id is 2) and the signal would be
19  SMP2P (signal-id is 2). The SMP2P itself falls under the Multiprocessor (MPROC)
20  protocol (protocol-id is 0). Refer include/dt-bindings/mailbox/qcom-ipcc.h
21  for the list of such IDs.
22
23properties:
24  compatible:
25    items:
26      - enum:
27          - qcom,sm8250-ipcc
28          - qcom,sm8350-ipcc
29          - qcom,sc7280-ipcc
30      - const: qcom,ipcc
31
32  reg:
33    maxItems: 1
34
35  interrupts:
36    maxItems: 1
37
38  interrupt-controller: true
39
40  "#interrupt-cells":
41    const: 3
42    description:
43      The first cell is the client-id, the second cell is the signal-id and the
44      third cell is the interrupt type.
45
46  "#mbox-cells":
47    const: 2
48    description:
49      The first cell is the client-id, and the second cell is the signal-id.
50
51required:
52  - compatible
53  - reg
54  - interrupts
55  - interrupt-controller
56  - "#interrupt-cells"
57  - "#mbox-cells"
58
59additionalProperties: false
60
61examples:
62  - |
63        #include <dt-bindings/interrupt-controller/arm-gic.h>
64        #include <dt-bindings/mailbox/qcom-ipcc.h>
65
66        mailbox@408000 {
67                compatible = "qcom,sm8250-ipcc", "qcom,ipcc";
68                reg = <0x408000 0x1000>;
69                interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>;
70                interrupt-controller;
71                #interrupt-cells = <3>;
72                #mbox-cells = <2>;
73        };
74
75        smp2p-modem {
76                compatible = "qcom,smp2p";
77                interrupts-extended = <&ipcc_mproc IPCC_CLIENT_MPSS
78                                IPCC_MPROC_SIGNAL_SMP2P IRQ_TYPE_EDGE_RISING>;
79                mboxes = <&ipcc_mproc IPCC_CLIENT_MPSS IPCC_MPROC_SIGNAL_SMP2P>;
80
81                /* Other SMP2P fields */
82        };
83