1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/mailbox/fsl,mu.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: NXP i.MX Messaging Unit (MU) 8 9maintainers: 10 - Dong Aisheng <aisheng.dong@nxp.com> 11 12description: | 13 The Messaging Unit module enables two processors within the SoC to 14 communicate and coordinate by passing messages (e.g. data, status 15 and control) through the MU interface. The MU also provides the ability 16 for one processor to signal the other processor using interrupts. 17 18 Because the MU manages the messaging between processors, the MU uses 19 different clocks (from each side of the different peripheral buses). 20 Therefore, the MU must synchronize the accesses from one side to the 21 other. The MU accomplishes synchronization using two sets of matching 22 registers (Processor A-facing, Processor B-facing). 23 24properties: 25 compatible: 26 oneOf: 27 - const: fsl,imx6sx-mu 28 - const: fsl,imx7ulp-mu 29 - const: fsl,imx8-mu-scu 30 - items: 31 - enum: 32 - fsl,imx7s-mu 33 - fsl,imx8mq-mu 34 - fsl,imx8mm-mu 35 - fsl,imx8mn-mu 36 - fsl,imx8mp-mu 37 - fsl,imx8qm-mu 38 - fsl,imx8qxp-mu 39 - const: fsl,imx6sx-mu 40 - description: To communicate with i.MX8 SCU with fast IPC 41 items: 42 - const: fsl,imx8-mu-scu 43 - enum: 44 - fsl,imx8qm-mu 45 - fsl,imx8qxp-mu 46 - const: fsl,imx6sx-mu 47 48 reg: 49 maxItems: 1 50 51 interrupts: 52 maxItems: 1 53 54 "#mbox-cells": 55 description: | 56 <&phandle type channel> 57 phandle : Label name of controller 58 type : Channel type 59 channel : Channel number 60 61 This MU support 4 type of unidirectional channels, each type 62 has 4 channels. A total of 16 channels. Following types are 63 supported: 64 0 - TX channel with 32bit transmit register and IRQ transmit 65 acknowledgment support. 66 1 - RX channel with 32bit receive register and IRQ support 67 2 - TX doorbell channel. Without own register and no ACK support. 68 3 - RX doorbell channel. 69 const: 2 70 71 clocks: 72 maxItems: 1 73 74 fsl,mu-side-b: 75 description: boolean, if present, means it is for side B MU. 76 type: boolean 77 78 power-domains: 79 maxItems: 1 80 81required: 82 - compatible 83 - reg 84 - interrupts 85 - "#mbox-cells" 86 87additionalProperties: false 88 89examples: 90 - | 91 #include <dt-bindings/interrupt-controller/arm-gic.h> 92 93 mailbox@5d1b0000 { 94 compatible = "fsl,imx8qxp-mu", "fsl,imx6sx-mu"; 95 reg = <0x5d1b0000 0x10000>; 96 interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>; 97 #mbox-cells = <2>; 98 }; 99