xref: /freebsd/sys/contrib/device-tree/Bindings/mailbox/fsl,mu.yaml (revision a03411e84728e9b267056fd31c7d1d9d1dc1b01e) 
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/mailbox/fsl,mu.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: NXP i.MX Messaging Unit (MU)
8
9maintainers:
10  - Dong Aisheng <aisheng.dong@nxp.com>
11
12description: |
13  The Messaging Unit module enables two processors within the SoC to
14  communicate and coordinate by passing messages (e.g. data, status
15  and control) through the MU interface. The MU also provides the ability
16  for one processor to signal the other processor using interrupts.
17
18  Because the MU manages the messaging between processors, the MU uses
19  different clocks (from each side of the different peripheral buses).
20  Therefore, the MU must synchronize the accesses from one side to the
21  other. The MU accomplishes synchronization using two sets of matching
22  registers (Processor A-facing, Processor B-facing).
23
24properties:
25  compatible:
26    oneOf:
27      - const: fsl,imx6sx-mu
28      - const: fsl,imx7ulp-mu
29      - const: fsl,imx8ulp-mu
30      - const: fsl,imx8-mu-scu
31      - const: fsl,imx8-mu-seco
32      - const: fsl,imx93-mu-s4
33      - const: fsl,imx8ulp-mu-s4
34      - items:
35          - const: fsl,imx93-mu
36          - const: fsl,imx8ulp-mu
37      - items:
38          - enum:
39              - fsl,imx7s-mu
40              - fsl,imx8mq-mu
41              - fsl,imx8mm-mu
42              - fsl,imx8mn-mu
43              - fsl,imx8mp-mu
44              - fsl,imx8qm-mu
45              - fsl,imx8qxp-mu
46          - const: fsl,imx6sx-mu
47      - description: To communicate with i.MX8 SCU with fast IPC
48        items:
49          - const: fsl,imx8-mu-scu
50          - enum:
51              - fsl,imx8qm-mu
52              - fsl,imx8qxp-mu
53          - const: fsl,imx6sx-mu
54
55  reg:
56    maxItems: 1
57
58  interrupts:
59    minItems: 1
60    maxItems: 2
61
62  interrupt-names:
63    minItems: 1
64    items:
65      - const: tx
66      - const: rx
67
68  "#mbox-cells":
69    description: |
70      <&phandle type channel>
71      phandle   : Label name of controller
72      type      : Channel type
73      channel   : Channel number
74
75      This MU support 5 type of unidirectional channels, each type
76      has 4 channels except RST channel which only has 1 channel.
77      A total of 17 channels.  Following types are
78      supported:
79      0 - TX channel with 32bit transmit register and IRQ transmit
80          acknowledgment support.
81      1 - RX channel with 32bit receive register and IRQ support
82      2 - TX doorbell channel. Without own register and no ACK support.
83      3 - RX doorbell channel.
84      4 - RST channel
85    const: 2
86
87  clocks:
88    maxItems: 1
89
90  fsl,mu-side-b:
91    description: boolean, if present, means it is for side B MU.
92    type: boolean
93
94  power-domains:
95    maxItems: 1
96
97required:
98  - compatible
99  - reg
100  - interrupts
101  - "#mbox-cells"
102
103allOf:
104  - if:
105      properties:
106        compatible:
107          enum:
108            - fsl,imx93-mu-s4
109    then:
110      properties:
111        interrupt-names:
112          minItems: 2
113        interrupts:
114          minItems: 2
115
116    else:
117      properties:
118        interrupts:
119          maxItems: 1
120      not:
121        required:
122          - interrupt-names
123
124additionalProperties: false
125
126examples:
127  - |
128    #include <dt-bindings/interrupt-controller/arm-gic.h>
129
130    mailbox@5d1b0000 {
131        compatible = "fsl,imx8qxp-mu", "fsl,imx6sx-mu";
132        reg = <0x5d1b0000 0x10000>;
133        interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>;
134        #mbox-cells = <2>;
135    };
136