1*c66ec88fSEmmanuel VadotThe PDC driver manages data transfer to and from various offload engines 2*c66ec88fSEmmanuel Vadoton some Broadcom SoCs. An SoC may have multiple PDC hardware blocks. There is 3*c66ec88fSEmmanuel Vadotone device tree entry per block. On some chips, the PDC functionality is 4*c66ec88fSEmmanuel Vadothandled by the FA2 (Northstar Plus). 5*c66ec88fSEmmanuel Vadot 6*c66ec88fSEmmanuel VadotRequired properties: 7*c66ec88fSEmmanuel Vadot- compatible : Should be "brcm,iproc-pdc-mbox" or "brcm,iproc-fa2-mbox" for 8*c66ec88fSEmmanuel Vadot FA2/Northstar Plus. 9*c66ec88fSEmmanuel Vadot- reg: Should contain PDC registers location and length. 10*c66ec88fSEmmanuel Vadot- interrupts: Should contain the IRQ line for the PDC. 11*c66ec88fSEmmanuel Vadot- #mbox-cells: 1 12*c66ec88fSEmmanuel Vadot- brcm,rx-status-len: Length of metadata preceding received frames, in bytes. 13*c66ec88fSEmmanuel Vadot 14*c66ec88fSEmmanuel VadotOptional properties: 15*c66ec88fSEmmanuel Vadot- brcm,use-bcm-hdr: present if a BCM header precedes each frame. 16*c66ec88fSEmmanuel Vadot 17*c66ec88fSEmmanuel VadotExample: 18*c66ec88fSEmmanuel Vadot pdc0: iproc-pdc0@612c0000 { 19*c66ec88fSEmmanuel Vadot compatible = "brcm,iproc-pdc-mbox"; 20*c66ec88fSEmmanuel Vadot reg = <0 0x612c0000 0 0x445>; /* PDC FS0 regs */ 21*c66ec88fSEmmanuel Vadot interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>; 22*c66ec88fSEmmanuel Vadot #mbox-cells = <1>; /* one cell per mailbox channel */ 23*c66ec88fSEmmanuel Vadot brcm,rx-status-len = <32>; 24*c66ec88fSEmmanuel Vadot brcm,use-bcm-hdr; 25*c66ec88fSEmmanuel Vadot }; 26