xref: /freebsd/sys/contrib/device-tree/Bindings/iommu/renesas,ipmmu-vmsa.yaml (revision cfd6422a5217410fbd66f7a7a8a64d9d85e61229) 
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/iommu/renesas,ipmmu-vmsa.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Renesas VMSA-Compatible IOMMU
8
9maintainers:
10  - Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
11
12description:
13  The IPMMU is an IOMMU implementation compatible with the ARM VMSA page tables.
14  It provides address translation for bus masters outside of the CPU, each
15  connected to the IPMMU through a port called micro-TLB.
16
17properties:
18  compatible:
19    oneOf:
20      - items:
21          - enum:
22              - renesas,ipmmu-r8a73a4  # R-Mobile APE6
23              - renesas,ipmmu-r8a7743  # RZ/G1M
24              - renesas,ipmmu-r8a7744  # RZ/G1N
25              - renesas,ipmmu-r8a7745  # RZ/G1E
26              - renesas,ipmmu-r8a7790  # R-Car H2
27              - renesas,ipmmu-r8a7791  # R-Car M2-W
28              - renesas,ipmmu-r8a7793  # R-Car M2-N
29              - renesas,ipmmu-r8a7794  # R-Car E2
30          - const: renesas,ipmmu-vmsa  # R-Mobile APE6 or R-Car Gen2 or RZ/G1
31      - items:
32          - enum:
33              - renesas,ipmmu-r8a774a1 # RZ/G2M
34              - renesas,ipmmu-r8a774b1 # RZ/G2N
35              - renesas,ipmmu-r8a774e1 # RZ/G2H
36              - renesas,ipmmu-r8a774c0 # RZ/G2E
37              - renesas,ipmmu-r8a7795  # R-Car H3
38              - renesas,ipmmu-r8a7796  # R-Car M3-W
39              - renesas,ipmmu-r8a77961 # R-Car M3-W+
40              - renesas,ipmmu-r8a77965 # R-Car M3-N
41              - renesas,ipmmu-r8a77970 # R-Car V3M
42              - renesas,ipmmu-r8a77980 # R-Car V3H
43              - renesas,ipmmu-r8a77990 # R-Car E3
44              - renesas,ipmmu-r8a77995 # R-Car D3
45
46  reg:
47    maxItems: 1
48
49  interrupts:
50    minItems: 1
51    maxItems: 2
52    description:
53      Specifiers for the MMU fault interrupts. Not required for cache IPMMUs.
54    items:
55      - description: non-secure mode
56      - description: secure mode if supported
57
58  '#iommu-cells':
59    const: 1
60    description:
61      The number of the micro-TLB that the device is connected to.
62
63  power-domains:
64    maxItems: 1
65
66  renesas,ipmmu-main:
67    $ref: /schemas/types.yaml#/definitions/phandle-array
68    description:
69      Reference to the main IPMMU phandle plus 1 cell. The cell is
70      the interrupt bit number associated with the particular cache IPMMU
71      device. The interrupt bit number needs to match the main IPMMU IMSSTR
72      register. Only used by cache IPMMU instances.
73
74required:
75  - compatible
76  - reg
77  - '#iommu-cells'
78  - power-domains
79
80oneOf:
81  - required:
82      - interrupts
83  - required:
84      - renesas,ipmmu-main
85
86additionalProperties: false
87
88examples:
89  - |
90    #include <dt-bindings/clock/r8a7791-cpg-mssr.h>
91    #include <dt-bindings/interrupt-controller/arm-gic.h>
92    #include <dt-bindings/power/r8a7791-sysc.h>
93
94    ipmmu_mx: iommu@fe951000 {
95        compatible = "renasas,ipmmu-r8a7791", "renasas,ipmmu-vmsa";
96        reg = <0xfe951000 0x1000>;
97        interrupts = <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>,
98                     <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
99        #iommu-cells = <1>;
100    };
101