xref: /freebsd/sys/contrib/device-tree/Bindings/iommu/renesas,ipmmu-vmsa.yaml (revision 6be3386466ab79a84b48429ae66244f21526d3df) 
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/iommu/renesas,ipmmu-vmsa.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Renesas VMSA-Compatible IOMMU
8
9maintainers:
10  - Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
11
12description:
13  The IPMMU is an IOMMU implementation compatible with the ARM VMSA page tables.
14  It provides address translation for bus masters outside of the CPU, each
15  connected to the IPMMU through a port called micro-TLB.
16
17properties:
18  compatible:
19    oneOf:
20      - items:
21          - enum:
22              - renesas,ipmmu-r8a73a4  # R-Mobile APE6
23              - renesas,ipmmu-r8a7742  # RZ/G1H
24              - renesas,ipmmu-r8a7743  # RZ/G1M
25              - renesas,ipmmu-r8a7744  # RZ/G1N
26              - renesas,ipmmu-r8a7745  # RZ/G1E
27              - renesas,ipmmu-r8a7790  # R-Car H2
28              - renesas,ipmmu-r8a7791  # R-Car M2-W
29              - renesas,ipmmu-r8a7793  # R-Car M2-N
30              - renesas,ipmmu-r8a7794  # R-Car E2
31          - const: renesas,ipmmu-vmsa  # R-Mobile APE6 or R-Car Gen2 or RZ/G1
32      - items:
33          - enum:
34              - renesas,ipmmu-r8a774a1 # RZ/G2M
35              - renesas,ipmmu-r8a774b1 # RZ/G2N
36              - renesas,ipmmu-r8a774c0 # RZ/G2E
37              - renesas,ipmmu-r8a774e1 # RZ/G2H
38              - renesas,ipmmu-r8a7795  # R-Car H3
39              - renesas,ipmmu-r8a7796  # R-Car M3-W
40              - renesas,ipmmu-r8a77961 # R-Car M3-W+
41              - renesas,ipmmu-r8a77965 # R-Car M3-N
42              - renesas,ipmmu-r8a77970 # R-Car V3M
43              - renesas,ipmmu-r8a77980 # R-Car V3H
44              - renesas,ipmmu-r8a77990 # R-Car E3
45              - renesas,ipmmu-r8a77995 # R-Car D3
46
47  reg:
48    maxItems: 1
49
50  interrupts:
51    minItems: 1
52    maxItems: 2
53    description:
54      Specifiers for the MMU fault interrupts. Not required for cache IPMMUs.
55    items:
56      - description: non-secure mode
57      - description: secure mode if supported
58
59  '#iommu-cells':
60    const: 1
61    description:
62      The number of the micro-TLB that the device is connected to.
63
64  power-domains:
65    maxItems: 1
66
67  renesas,ipmmu-main:
68    $ref: /schemas/types.yaml#/definitions/phandle-array
69    description:
70      Reference to the main IPMMU phandle plus 1 cell. The cell is
71      the interrupt bit number associated with the particular cache IPMMU
72      device. The interrupt bit number needs to match the main IPMMU IMSSTR
73      register. Only used by cache IPMMU instances.
74
75required:
76  - compatible
77  - reg
78  - '#iommu-cells'
79  - power-domains
80
81oneOf:
82  - required:
83      - interrupts
84  - required:
85      - renesas,ipmmu-main
86
87additionalProperties: false
88
89examples:
90  - |
91    #include <dt-bindings/clock/r8a7791-cpg-mssr.h>
92    #include <dt-bindings/interrupt-controller/arm-gic.h>
93    #include <dt-bindings/power/r8a7791-sysc.h>
94
95    ipmmu_mx: iommu@fe951000 {
96        compatible = "renasas,ipmmu-r8a7791", "renasas,ipmmu-vmsa";
97        reg = <0xfe951000 0x1000>;
98        interrupts = <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>,
99                     <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
100        #iommu-cells = <1>;
101    };
102