xref: /freebsd/sys/contrib/device-tree/Bindings/iommu/qcom,apq8064-iommu.yaml (revision 0e8011faf58b743cc652e3b2ad0f7671227610df)

# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---

$id: http://devicetree.org/schemas/iommu/qcom,apq8064-iommu.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Qualcomm APQ8064 IOMMU

maintainers:
  - David Heidelberg <david@ixit.cz>

description:
  The MSM IOMMU is an implementation compatible with the ARM VMSA short
  descriptor page tables. It provides address translation for bus masters
  outside of the CPU, each connected to the IOMMU through a port called micro-TLB.

properties:
  compatible:
    const: qcom,apq8064-iommu

  clocks:
    items:
      - description: interface clock for register accesses
      - description: functional clock for bus accesses

  clock-names:
    items:
      - const: smmu_pclk
      - const: iommu_clk

  reg:
    maxItems: 1

  interrupts:
    description: Specifiers for the MMU fault interrupts.
    minItems: 1
    items:
      - description: non-secure mode interrupt
      - description: secure mode interrupt (for instances which supports it)

  "#iommu-cells":
    const: 1
    description: Each IOMMU specifier describes a single Stream ID.

  qcom,ncb:
    $ref: /schemas/types.yaml#/definitions/uint32
    description: The total number of context banks in the IOMMU.
    minimum: 1
    maximum: 4

required:
  - reg
  - interrupts
  - clocks
  - clock-names
  - qcom,ncb

additionalProperties: false

examples:
  - |
    #include <dt-bindings/clock/qcom,mmcc-msm8960.h>
    #include <dt-bindings/interrupt-controller/irq.h>
    #include <dt-bindings/interrupt-controller/arm-gic.h>

    iommu@7500000 {
            compatible = "qcom,apq8064-iommu";
            reg = <0x07500000 0x100000>;
            interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>,
                         <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
            clocks = <&clk SMMU_AHB_CLK>,
                     <&clk MDP_AXI_CLK>;
            clock-names = "smmu_pclk",
                          "iommu_clk";
            #iommu-cells = <1>;
            qcom,ncb = <2>;
    };