1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/iommu/mediatek,iommu.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: MediaTek IOMMU Architecture Implementation 8 9maintainers: 10 - Yong Wu <yong.wu@mediatek.com> 11 12description: |+ 13 Some MediaTek SOCs contain a Multimedia Memory Management Unit (M4U), and 14 this M4U have two generations of HW architecture. Generation one uses flat 15 pagetable, and only supports 4K size page mapping. Generation two uses the 16 ARM Short-Descriptor translation table format for address translation. 17 18 About the M4U Hardware Block Diagram, please check below: 19 20 EMI (External Memory Interface) 21 | 22 m4u (Multimedia Memory Management Unit) 23 | 24 +--------+ 25 | | 26 gals0-rx gals1-rx (Global Async Local Sync rx) 27 | | 28 | | 29 gals0-tx gals1-tx (Global Async Local Sync tx) 30 | | Some SoCs may have GALS. 31 +--------+ 32 | 33 SMI Common(Smart Multimedia Interface Common) 34 | 35 +----------------+------- 36 | | 37 | gals-rx There may be GALS in some larbs. 38 | | 39 | | 40 | gals-tx 41 | | 42 SMI larb0 SMI larb1 ... SoCs have several SMI local arbiter(larb). 43 (display) (vdec) 44 | | 45 | | 46 +-----+-----+ +----+----+ 47 | | | | | | 48 | | |... | | | ... There are different ports in each larb. 49 | | | | | | 50 OVL0 RDMA0 WDMA0 MC PP VLD 51 52 As above, The Multimedia HW will go through SMI and M4U while it 53 access EMI. SMI is a bridge between m4u and the Multimedia HW. It contain 54 smi local arbiter and smi common. It will control whether the Multimedia 55 HW should go though the m4u for translation or bypass it and talk 56 directly with EMI. And also SMI help control the power domain and clocks for 57 each local arbiter. 58 59 Normally we specify a local arbiter(larb) for each multimedia HW 60 like display, video decode, and camera. And there are different ports 61 in each larb. Take a example, There are many ports like MC, PP, VLD in the 62 video decode local arbiter, all these ports are according to the video HW. 63 64 In some SoCs, there may be a GALS(Global Async Local Sync) module between 65 smi-common and m4u, and additional GALS module between smi-larb and 66 smi-common. GALS can been seen as a "asynchronous fifo" which could help 67 synchronize for the modules in different clock frequency. 68 69properties: 70 compatible: 71 oneOf: 72 - enum: 73 - mediatek,mt2701-m4u # generation one 74 - mediatek,mt2712-m4u # generation two 75 - mediatek,mt6779-m4u # generation two 76 - mediatek,mt8167-m4u # generation two 77 - mediatek,mt8173-m4u # generation two 78 - mediatek,mt8183-m4u # generation two 79 - mediatek,mt8186-iommu-mm # generation two 80 - mediatek,mt8192-m4u # generation two 81 - mediatek,mt8195-iommu-vdo # generation two 82 - mediatek,mt8195-iommu-vpp # generation two 83 - mediatek,mt8195-iommu-infra # generation two 84 85 - description: mt7623 generation one 86 items: 87 - const: mediatek,mt7623-m4u 88 - const: mediatek,mt2701-m4u 89 90 reg: 91 maxItems: 1 92 93 interrupts: 94 maxItems: 1 95 96 clocks: 97 items: 98 - description: bclk is the block clock. 99 100 clock-names: 101 items: 102 - const: bclk 103 104 mediatek,infracfg: 105 $ref: /schemas/types.yaml#/definitions/phandle 106 description: The phandle to the mediatek infracfg syscon 107 108 mediatek,larbs: 109 $ref: /schemas/types.yaml#/definitions/phandle-array 110 minItems: 1 111 maxItems: 32 112 items: 113 maxItems: 1 114 description: | 115 List of phandle to the local arbiters in the current Socs. 116 Refer to bindings/memory-controllers/mediatek,smi-larb.yaml. It must sort 117 according to the local arbiter index, like larb0, larb1, larb2... 118 119 '#iommu-cells': 120 const: 1 121 description: | 122 This is the mtk_m4u_id according to the HW. Specifies the mtk_m4u_id as 123 defined in 124 dt-binding/memory/mt2701-larb-port.h for mt2701 and mt7623, 125 dt-binding/memory/mt2712-larb-port.h for mt2712, 126 dt-binding/memory/mt6779-larb-port.h for mt6779, 127 dt-binding/memory/mt8167-larb-port.h for mt8167, 128 dt-binding/memory/mt8173-larb-port.h for mt8173, 129 dt-binding/memory/mt8183-larb-port.h for mt8183, 130 dt-binding/memory/mt8186-memory-port.h for mt8186, 131 dt-binding/memory/mt8192-larb-port.h for mt8192. 132 dt-binding/memory/mt8195-memory-port.h for mt8195. 133 134 power-domains: 135 maxItems: 1 136 137required: 138 - compatible 139 - reg 140 - interrupts 141 - '#iommu-cells' 142 143allOf: 144 - if: 145 properties: 146 compatible: 147 contains: 148 enum: 149 - mediatek,mt2701-m4u 150 - mediatek,mt2712-m4u 151 - mediatek,mt8173-m4u 152 - mediatek,mt8186-iommu-mm 153 - mediatek,mt8192-m4u 154 - mediatek,mt8195-iommu-vdo 155 - mediatek,mt8195-iommu-vpp 156 157 then: 158 required: 159 - clocks 160 161 - if: 162 properties: 163 compatible: 164 enum: 165 - mediatek,mt8186-iommu-mm 166 - mediatek,mt8192-m4u 167 - mediatek,mt8195-iommu-vdo 168 - mediatek,mt8195-iommu-vpp 169 170 then: 171 required: 172 - power-domains 173 174 - if: 175 properties: 176 compatible: 177 contains: 178 enum: 179 - mediatek,mt2712-m4u 180 - mediatek,mt8173-m4u 181 182 then: 183 required: 184 - mediatek,infracfg 185 186 - if: # The IOMMUs don't have larbs. 187 not: 188 properties: 189 compatible: 190 contains: 191 const: mediatek,mt8195-iommu-infra 192 193 then: 194 required: 195 - mediatek,larbs 196 197additionalProperties: false 198 199examples: 200 - | 201 #include <dt-bindings/clock/mt8173-clk.h> 202 #include <dt-bindings/interrupt-controller/arm-gic.h> 203 204 iommu: iommu@10205000 { 205 compatible = "mediatek,mt8173-m4u"; 206 reg = <0x10205000 0x1000>; 207 interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_LOW>; 208 clocks = <&infracfg CLK_INFRA_M4U>; 209 clock-names = "bclk"; 210 mediatek,infracfg = <&infracfg>; 211 mediatek,larbs = <&larb0>, <&larb1>, <&larb2>, 212 <&larb3>, <&larb4>, <&larb5>; 213 #iommu-cells = <1>; 214 }; 215