1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/iommu/mediatek,iommu.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: MediaTek IOMMU Architecture Implementation 8 9maintainers: 10 - Yong Wu <yong.wu@mediatek.com> 11 12description: |+ 13 Some MediaTek SOCs contain a Multimedia Memory Management Unit (M4U), and 14 this M4U have two generations of HW architecture. Generation one uses flat 15 pagetable, and only supports 4K size page mapping. Generation two uses the 16 ARM Short-Descriptor translation table format for address translation. 17 18 About the M4U Hardware Block Diagram, please check below: 19 20 EMI (External Memory Interface) 21 | 22 m4u (Multimedia Memory Management Unit) 23 | 24 +--------+ 25 | | 26 gals0-rx gals1-rx (Global Async Local Sync rx) 27 | | 28 | | 29 gals0-tx gals1-tx (Global Async Local Sync tx) 30 | | Some SoCs may have GALS. 31 +--------+ 32 | 33 SMI Common(Smart Multimedia Interface Common) 34 | 35 +----------------+------- 36 | | 37 | gals-rx There may be GALS in some larbs. 38 | | 39 | | 40 | gals-tx 41 | | 42 SMI larb0 SMI larb1 ... SoCs have several SMI local arbiter(larb). 43 (display) (vdec) 44 | | 45 | | 46 +-----+-----+ +----+----+ 47 | | | | | | 48 | | |... | | | ... There are different ports in each larb. 49 | | | | | | 50 OVL0 RDMA0 WDMA0 MC PP VLD 51 52 As above, The Multimedia HW will go through SMI and M4U while it 53 access EMI. SMI is a bridge between m4u and the Multimedia HW. It contain 54 smi local arbiter and smi common. It will control whether the Multimedia 55 HW should go though the m4u for translation or bypass it and talk 56 directly with EMI. And also SMI help control the power domain and clocks for 57 each local arbiter. 58 59 Normally we specify a local arbiter(larb) for each multimedia HW 60 like display, video decode, and camera. And there are different ports 61 in each larb. Take a example, There are many ports like MC, PP, VLD in the 62 video decode local arbiter, all these ports are according to the video HW. 63 64 In some SoCs, there may be a GALS(Global Async Local Sync) module between 65 smi-common and m4u, and additional GALS module between smi-larb and 66 smi-common. GALS can been seen as a "asynchronous fifo" which could help 67 synchronize for the modules in different clock frequency. 68 69properties: 70 compatible: 71 oneOf: 72 - enum: 73 - mediatek,mt2701-m4u # generation one 74 - mediatek,mt2712-m4u # generation two 75 - mediatek,mt6779-m4u # generation two 76 - mediatek,mt8167-m4u # generation two 77 - mediatek,mt8173-m4u # generation two 78 - mediatek,mt8183-m4u # generation two 79 - mediatek,mt8192-m4u # generation two 80 81 - description: mt7623 generation one 82 items: 83 - const: mediatek,mt7623-m4u 84 - const: mediatek,mt2701-m4u 85 86 reg: 87 maxItems: 1 88 89 interrupts: 90 maxItems: 1 91 92 clocks: 93 items: 94 - description: bclk is the block clock. 95 96 clock-names: 97 items: 98 - const: bclk 99 100 mediatek,larbs: 101 $ref: /schemas/types.yaml#/definitions/phandle-array 102 minItems: 1 103 maxItems: 32 104 items: 105 maxItems: 1 106 description: | 107 List of phandle to the local arbiters in the current Socs. 108 Refer to bindings/memory-controllers/mediatek,smi-larb.yaml. It must sort 109 according to the local arbiter index, like larb0, larb1, larb2... 110 111 '#iommu-cells': 112 const: 1 113 description: | 114 This is the mtk_m4u_id according to the HW. Specifies the mtk_m4u_id as 115 defined in 116 dt-binding/memory/mt2701-larb-port.h for mt2701 and mt7623, 117 dt-binding/memory/mt2712-larb-port.h for mt2712, 118 dt-binding/memory/mt6779-larb-port.h for mt6779, 119 dt-binding/memory/mt8167-larb-port.h for mt8167, 120 dt-binding/memory/mt8173-larb-port.h for mt8173, 121 dt-binding/memory/mt8183-larb-port.h for mt8183, 122 dt-binding/memory/mt8192-larb-port.h for mt8192. 123 124 power-domains: 125 maxItems: 1 126 127required: 128 - compatible 129 - reg 130 - interrupts 131 - mediatek,larbs 132 - '#iommu-cells' 133 134allOf: 135 - if: 136 properties: 137 compatible: 138 contains: 139 enum: 140 - mediatek,mt2701-m4u 141 - mediatek,mt2712-m4u 142 - mediatek,mt8173-m4u 143 - mediatek,mt8192-m4u 144 145 then: 146 required: 147 - clocks 148 149 - if: 150 properties: 151 compatible: 152 enum: 153 - mediatek,mt8192-m4u 154 155 then: 156 required: 157 - power-domains 158 159additionalProperties: false 160 161examples: 162 - | 163 #include <dt-bindings/clock/mt8173-clk.h> 164 #include <dt-bindings/interrupt-controller/arm-gic.h> 165 166 iommu: iommu@10205000 { 167 compatible = "mediatek,mt8173-m4u"; 168 reg = <0x10205000 0x1000>; 169 interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_LOW>; 170 clocks = <&infracfg CLK_INFRA_M4U>; 171 clock-names = "bclk"; 172 mediatek,larbs = <&larb0>, <&larb1>, <&larb2>, 173 <&larb3>, <&larb4>, <&larb5>; 174 #iommu-cells = <1>; 175 }; 176 177 - | 178 #include <dt-bindings/memory/mt8173-larb-port.h> 179 180 /* Example for a client device */ 181 display { 182 compatible = "mediatek,mt8173-disp"; 183 iommus = <&iommu M4U_PORT_DISP_OVL0>, 184 <&iommu M4U_PORT_DISP_RDMA0>; 185 }; 186