1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/iommu/mediatek,iommu.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: MediaTek IOMMU Architecture Implementation 8 9maintainers: 10 - Yong Wu <yong.wu@mediatek.com> 11 12description: |+ 13 Some MediaTek SOCs contain a Multimedia Memory Management Unit (M4U), and 14 this M4U have two generations of HW architecture. Generation one uses flat 15 pagetable, and only supports 4K size page mapping. Generation two uses the 16 ARM Short-Descriptor translation table format for address translation. 17 18 About the M4U Hardware Block Diagram, please check below: 19 20 EMI (External Memory Interface) 21 | 22 m4u (Multimedia Memory Management Unit) 23 | 24 +--------+ 25 | | 26 gals0-rx gals1-rx (Global Async Local Sync rx) 27 | | 28 | | 29 gals0-tx gals1-tx (Global Async Local Sync tx) 30 | | Some SoCs may have GALS. 31 +--------+ 32 | 33 SMI Common(Smart Multimedia Interface Common) 34 | 35 +----------------+------- 36 | | 37 | gals-rx There may be GALS in some larbs. 38 | | 39 | | 40 | gals-tx 41 | | 42 SMI larb0 SMI larb1 ... SoCs have several SMI local arbiter(larb). 43 (display) (vdec) 44 | | 45 | | 46 +-----+-----+ +----+----+ 47 | | | | | | 48 | | |... | | | ... There are different ports in each larb. 49 | | | | | | 50 OVL0 RDMA0 WDMA0 MC PP VLD 51 52 As above, The Multimedia HW will go through SMI and M4U while it 53 access EMI. SMI is a bridge between m4u and the Multimedia HW. It contain 54 smi local arbiter and smi common. It will control whether the Multimedia 55 HW should go though the m4u for translation or bypass it and talk 56 directly with EMI. And also SMI help control the power domain and clocks for 57 each local arbiter. 58 59 Normally we specify a local arbiter(larb) for each multimedia HW 60 like display, video decode, and camera. And there are different ports 61 in each larb. Take a example, There are many ports like MC, PP, VLD in the 62 video decode local arbiter, all these ports are according to the video HW. 63 64 In some SoCs, there may be a GALS(Global Async Local Sync) module between 65 smi-common and m4u, and additional GALS module between smi-larb and 66 smi-common. GALS can been seen as a "asynchronous fifo" which could help 67 synchronize for the modules in different clock frequency. 68 69properties: 70 compatible: 71 oneOf: 72 - enum: 73 - mediatek,mt2701-m4u # generation one 74 - mediatek,mt2712-m4u # generation two 75 - mediatek,mt6779-m4u # generation two 76 - mediatek,mt6795-m4u # generation two 77 - mediatek,mt8167-m4u # generation two 78 - mediatek,mt8173-m4u # generation two 79 - mediatek,mt8183-m4u # generation two 80 - mediatek,mt8186-iommu-mm # generation two 81 - mediatek,mt8192-m4u # generation two 82 - mediatek,mt8195-iommu-vdo # generation two 83 - mediatek,mt8195-iommu-vpp # generation two 84 - mediatek,mt8195-iommu-infra # generation two 85 - mediatek,mt8365-m4u # generation two 86 87 - description: mt7623 generation one 88 items: 89 - const: mediatek,mt7623-m4u 90 - const: mediatek,mt2701-m4u 91 92 reg: 93 maxItems: 1 94 95 interrupts: 96 maxItems: 1 97 98 clocks: 99 items: 100 - description: bclk is the block clock. 101 102 clock-names: 103 items: 104 - const: bclk 105 106 mediatek,infracfg: 107 $ref: /schemas/types.yaml#/definitions/phandle 108 description: The phandle to the mediatek infracfg syscon 109 110 mediatek,larbs: 111 $ref: /schemas/types.yaml#/definitions/phandle-array 112 minItems: 1 113 maxItems: 32 114 items: 115 maxItems: 1 116 description: | 117 List of phandle to the local arbiters in the current Socs. 118 Refer to bindings/memory-controllers/mediatek,smi-larb.yaml. It must sort 119 according to the local arbiter index, like larb0, larb1, larb2... 120 121 '#iommu-cells': 122 const: 1 123 description: | 124 This is the mtk_m4u_id according to the HW. Specifies the mtk_m4u_id as 125 defined in 126 dt-binding/memory/mt2701-larb-port.h for mt2701 and mt7623, 127 dt-binding/memory/mt2712-larb-port.h for mt2712, 128 dt-binding/memory/mt6779-larb-port.h for mt6779, 129 dt-binding/memory/mt6795-larb-port.h for mt6795, 130 dt-binding/memory/mt8167-larb-port.h for mt8167, 131 dt-binding/memory/mt8173-larb-port.h for mt8173, 132 dt-binding/memory/mt8183-larb-port.h for mt8183, 133 dt-binding/memory/mt8186-memory-port.h for mt8186, 134 dt-binding/memory/mt8192-larb-port.h for mt8192. 135 dt-binding/memory/mt8195-memory-port.h for mt8195. 136 dt-binding/memory/mediatek,mt8365-larb-port.h for mt8365. 137 138 power-domains: 139 maxItems: 1 140 141required: 142 - compatible 143 - reg 144 - interrupts 145 - '#iommu-cells' 146 147allOf: 148 - if: 149 properties: 150 compatible: 151 contains: 152 enum: 153 - mediatek,mt2701-m4u 154 - mediatek,mt2712-m4u 155 - mediatek,mt6795-m4u 156 - mediatek,mt8173-m4u 157 - mediatek,mt8186-iommu-mm 158 - mediatek,mt8192-m4u 159 - mediatek,mt8195-iommu-vdo 160 - mediatek,mt8195-iommu-vpp 161 162 then: 163 required: 164 - clocks 165 166 - if: 167 properties: 168 compatible: 169 enum: 170 - mediatek,mt8186-iommu-mm 171 - mediatek,mt8192-m4u 172 - mediatek,mt8195-iommu-vdo 173 - mediatek,mt8195-iommu-vpp 174 175 then: 176 required: 177 - power-domains 178 179 - if: 180 properties: 181 compatible: 182 contains: 183 enum: 184 - mediatek,mt2712-m4u 185 - mediatek,mt6795-m4u 186 - mediatek,mt8173-m4u 187 188 then: 189 required: 190 - mediatek,infracfg 191 192 - if: # The IOMMUs don't have larbs. 193 not: 194 properties: 195 compatible: 196 contains: 197 const: mediatek,mt8195-iommu-infra 198 199 then: 200 required: 201 - mediatek,larbs 202 203additionalProperties: false 204 205examples: 206 - | 207 #include <dt-bindings/clock/mt8173-clk.h> 208 #include <dt-bindings/interrupt-controller/arm-gic.h> 209 210 iommu: iommu@10205000 { 211 compatible = "mediatek,mt8173-m4u"; 212 reg = <0x10205000 0x1000>; 213 interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_LOW>; 214 clocks = <&infracfg CLK_INFRA_M4U>; 215 clock-names = "bclk"; 216 mediatek,infracfg = <&infracfg>; 217 mediatek,larbs = <&larb0>, <&larb1>, <&larb2>, 218 <&larb3>, <&larb4>, <&larb5>; 219 #iommu-cells = <1>; 220 }; 221