1# SPDX-License-Identifier: GPL-2.0-only 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/iommu/arm,smmu.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: ARM System MMU Architecture Implementation 8 9maintainers: 10 - Will Deacon <will@kernel.org> 11 - Robin Murphy <Robin.Murphy@arm.com> 12 13description: |+ 14 ARM SoCs may contain an implementation of the ARM System Memory 15 Management Unit Architecture, which can be used to provide 1 or 2 stages 16 of address translation to bus masters external to the CPU. 17 18 The SMMU may also raise interrupts in response to various fault 19 conditions. 20 21properties: 22 $nodename: 23 pattern: "^iommu@[0-9a-f]*" 24 compatible: 25 oneOf: 26 - description: Qcom SoCs implementing "arm,smmu-v2" 27 items: 28 - enum: 29 - qcom,msm8996-smmu-v2 30 - qcom,msm8998-smmu-v2 31 - const: qcom,smmu-v2 32 33 - description: Qcom SoCs implementing "arm,mmu-500" 34 items: 35 - enum: 36 - qcom,qcm2290-smmu-500 37 - qcom,sc7180-smmu-500 38 - qcom,sc7280-smmu-500 39 - qcom,sc8180x-smmu-500 40 - qcom,sdm845-smmu-500 41 - qcom,sdx55-smmu-500 42 - qcom,sm6350-smmu-500 43 - qcom,sm8150-smmu-500 44 - qcom,sm8250-smmu-500 45 - qcom,sm8350-smmu-500 46 - qcom,sm8450-smmu-500 47 - const: arm,mmu-500 48 - description: Qcom Adreno GPUs implementing "arm,smmu-v2" 49 items: 50 - enum: 51 - qcom,sc7180-smmu-v2 52 - qcom,sdm845-smmu-v2 53 - const: qcom,adreno-smmu 54 - const: qcom,smmu-v2 55 - description: Marvell SoCs implementing "arm,mmu-500" 56 items: 57 - const: marvell,ap806-smmu-500 58 - const: arm,mmu-500 59 - description: NVIDIA SoCs that require memory controller interaction 60 and may program multiple ARM MMU-500s identically with the memory 61 controller interleaving translations between multiple instances 62 for improved performance. 63 items: 64 - enum: 65 - nvidia,tegra194-smmu 66 - nvidia,tegra186-smmu 67 - const: nvidia,smmu-500 68 - items: 69 - const: arm,mmu-500 70 - const: arm,smmu-v2 71 - items: 72 - enum: 73 - arm,mmu-400 74 - arm,mmu-401 75 - const: arm,smmu-v1 76 - enum: 77 - arm,smmu-v1 78 - arm,smmu-v2 79 - arm,mmu-400 80 - arm,mmu-401 81 - arm,mmu-500 82 - cavium,smmu-v2 83 84 reg: 85 minItems: 1 86 maxItems: 2 87 88 '#global-interrupts': 89 description: The number of global interrupts exposed by the device. 90 $ref: /schemas/types.yaml#/definitions/uint32 91 minimum: 0 92 maximum: 260 # 2 secure, 2 non-secure, and up to 256 perf counters 93 94 '#iommu-cells': 95 enum: [ 1, 2 ] 96 description: | 97 See Documentation/devicetree/bindings/iommu/iommu.txt for details. With a 98 value of 1, each IOMMU specifier represents a distinct stream ID emitted 99 by that device into the relevant SMMU. 100 101 SMMUs with stream matching support and complex masters may use a value of 102 2, where the second cell of the IOMMU specifier represents an SMR mask to 103 combine with the ID in the first cell. Care must be taken to ensure the 104 set of matched IDs does not result in conflicts. 105 106 interrupts: 107 minItems: 1 108 maxItems: 388 # 260 plus 128 contexts 109 description: | 110 Interrupt list, with the first #global-interrupts entries corresponding to 111 the global interrupts and any following entries corresponding to context 112 interrupts, specified in order of their indexing by the SMMU. 113 114 For SMMUv2 implementations, there must be exactly one interrupt per 115 context bank. In the case of a single, combined interrupt, it must be 116 listed multiple times. 117 118 dma-coherent: 119 description: | 120 Present if page table walks made by the SMMU are cache coherent with the 121 CPU. 122 123 NOTE: this only applies to the SMMU itself, not masters connected 124 upstream of the SMMU. 125 126 calxeda,smmu-secure-config-access: 127 type: boolean 128 description: 129 Enable proper handling of buggy implementations that always use secure 130 access to SMMU configuration registers. In this case non-secure aliases of 131 secure registers have to be used during SMMU configuration. 132 133 stream-match-mask: 134 $ref: /schemas/types.yaml#/definitions/uint32 135 description: | 136 For SMMUs supporting stream matching and using #iommu-cells = <1>, 137 specifies a mask of bits to ignore when matching stream IDs (e.g. this may 138 be programmed into the SMRn.MASK field of every stream match register 139 used). For cases where it is desirable to ignore some portion of every 140 Stream ID (e.g. for certain MMU-500 configurations given globally unique 141 input IDs). This property is not valid for SMMUs using stream indexing, or 142 using stream matching with #iommu-cells = <2>, and may be ignored if 143 present in such cases. 144 145 clock-names: 146 items: 147 - const: bus 148 - const: iface 149 150 clocks: 151 items: 152 - description: bus clock required for downstream bus access and for the 153 smmu ptw 154 - description: interface clock required to access smmu's registers 155 through the TCU's programming interface. 156 157 power-domains: 158 maxItems: 1 159 160required: 161 - compatible 162 - reg 163 - '#global-interrupts' 164 - '#iommu-cells' 165 - interrupts 166 167additionalProperties: false 168 169allOf: 170 - if: 171 properties: 172 compatible: 173 contains: 174 enum: 175 - nvidia,tegra194-smmu 176 - nvidia,tegra186-smmu 177 then: 178 properties: 179 reg: 180 minItems: 1 181 maxItems: 2 182 else: 183 properties: 184 reg: 185 maxItems: 1 186 187examples: 188 - |+ 189 /* SMMU with stream matching or stream indexing */ 190 smmu1: iommu@ba5e0000 { 191 compatible = "arm,smmu-v1"; 192 reg = <0xba5e0000 0x10000>; 193 #global-interrupts = <2>; 194 interrupts = <0 32 4>, 195 <0 33 4>, 196 <0 34 4>, /* This is the first context interrupt */ 197 <0 35 4>, 198 <0 36 4>, 199 <0 37 4>; 200 #iommu-cells = <1>; 201 }; 202 203 /* device with two stream IDs, 0 and 7 */ 204 master1 { 205 iommus = <&smmu1 0>, 206 <&smmu1 7>; 207 }; 208 209 210 /* SMMU with stream matching */ 211 smmu2: iommu@ba5f0000 { 212 compatible = "arm,smmu-v1"; 213 reg = <0xba5f0000 0x10000>; 214 #global-interrupts = <2>; 215 interrupts = <0 38 4>, 216 <0 39 4>, 217 <0 40 4>, /* This is the first context interrupt */ 218 <0 41 4>, 219 <0 42 4>, 220 <0 43 4>; 221 #iommu-cells = <2>; 222 }; 223 224 /* device with stream IDs 0 and 7 */ 225 master2 { 226 iommus = <&smmu2 0 0>, 227 <&smmu2 7 0>; 228 }; 229 230 /* device with stream IDs 1, 17, 33 and 49 */ 231 master3 { 232 iommus = <&smmu2 1 0x30>; 233 }; 234 235 236 /* ARM MMU-500 with 10-bit stream ID input configuration */ 237 smmu3: iommu@ba600000 { 238 compatible = "arm,mmu-500", "arm,smmu-v2"; 239 reg = <0xba600000 0x10000>; 240 #global-interrupts = <2>; 241 interrupts = <0 44 4>, 242 <0 45 4>, 243 <0 46 4>, /* This is the first context interrupt */ 244 <0 47 4>, 245 <0 48 4>, 246 <0 49 4>; 247 #iommu-cells = <1>; 248 /* always ignore appended 5-bit TBU number */ 249 stream-match-mask = <0x7c00>; 250 }; 251 252 bus { 253 /* bus whose child devices emit one unique 10-bit stream 254 ID each, but may master through multiple SMMU TBUs */ 255 iommu-map = <0 &smmu3 0 0x400>; 256 257 258 }; 259 260 - |+ 261 /* Qcom's arm,smmu-v2 implementation */ 262 #include <dt-bindings/interrupt-controller/arm-gic.h> 263 #include <dt-bindings/interrupt-controller/irq.h> 264 smmu4: iommu@d00000 { 265 compatible = "qcom,msm8996-smmu-v2", "qcom,smmu-v2"; 266 reg = <0xd00000 0x10000>; 267 268 #global-interrupts = <1>; 269 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>, 270 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 271 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>; 272 #iommu-cells = <1>; 273 power-domains = <&mmcc 0>; 274 275 clocks = <&mmcc 123>, 276 <&mmcc 124>; 277 clock-names = "bus", "iface"; 278 }; 279